finFET

August 23, 2021

IEDM 2021 publishes course schedule

Aiming for a primarily physical event in the fall, organisers of the 2021 IEDM have published the tutorial and short-core schedule.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
June 4, 2021

TSMC spins outs processes for automotive and RF

TSMC is developing processes for high-end automotive and RF based off its N5 and N7 families.
Article  |  Topics: Blog Topics  |  Tags: , , , , , ,   |  Organizations:
December 15, 2020

Chipmaking’s new environment presented at IEDM

Imec's senior vice president of CMOS outlined future directions for the technology over the coming decade.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
August 25, 2020

TSMC fills in sub-nodes as EUV gains ground

TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , , ,   |  Organizations: ,
May 26, 2020

Nanometer scaling puts focus on power at VLSI in June

Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: , , , ,
August 27, 2019

GlobalFoundries takes aim at TSMC’s customers in patent action

GlobalFoundries is calling for imports of chips fabbed by TSMC into the US and Germany in multiple actions based on a list of 16 patents.
Article  |  Topics: Blog - IP  |  Tags: , , , ,   |  Organizations: , , ,
February 28, 2019

Graphcore licenses ESD protection from Sofics

Graphcore has licensed IP from Belgium-based Sofics to protect its Colossus GC2 processors from ESD.
Article  |  Topics: Blog - IP  |  Tags: , , ,
August 28, 2018

GlobalFoundries stops 7nm work to focus on existing processes

GlobalFoundries has decided to put development of its 7nm process on the backburner and focus on its existing finFET and FD-SOI processes.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , , ,   |  Organizations:
June 25, 2018

Node-variant FinFET tweaks try to improve cost, performance

Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations: , ,
June 21, 2018

Samsung couples EUV with DTCO for 7nm shrink

Samsung Electronics expects to increase savings on die area in the shift from its 10nm to 7nm node by applying both EUV for critical layers and several layout-focused process changes.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors