finFET

August 27, 2019

GlobalFoundries takes aim at TSMC’s customers in patent action

GlobalFoundries is calling for imports of chips fabbed by TSMC into the US and Germany in multiple actions based on a list of 16 patents.
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February 28, 2019

Graphcore licenses ESD protection from Sofics

Graphcore has licensed IP from Belgium-based Sofics to protect its Colossus GC2 processors from ESD.
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August 28, 2018

GlobalFoundries stops 7nm work to focus on existing processes

GlobalFoundries has decided to put development of its 7nm process on the backburner and focus on its existing finFET and FD-SOI processes.
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June 25, 2018

Node-variant FinFET tweaks try to improve cost, performance

Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.
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June 21, 2018

Samsung couples EUV with DTCO for 7nm shrink

Samsung Electronics expects to increase savings on die area in the shift from its 10nm to 7nm node by applying both EUV for critical layers and several layout-focused process changes.
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June 20, 2018

SAR-VCO combo tunes RF receiver power on 16nm

Researchers from the UC Berkeley and Intel teamed up to develop an energy-tuneable RF front-end on a digital finFET process with no need for analog process options.
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May 11, 2018

Mixed-signal circuits push scaled CMOS at VLSI

The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.
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May 4, 2018

7nm process with EUV to feature at VLSI

Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
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April 10, 2018

Cadence tunes Virtuoso for 5nm and SIP

Cadence Design Systems has made enhancements to its Virtuoso mixed-signal layout tool at both the system-level and nanometer-design levels for its 18.1 release.
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January 2, 2018

Watch out for layout effects on finFET reliability

As geometries have shrunk, layout-dependent effects in CMOS have become ever more problematic. They are not just popping up in performance but reliability and aging effects as one IEDM presentation showed.
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