VLSI to explore vertical device changes and 3nm finFET
The upcoming VLSI Symposium will examine progress in using backside contacts and 3D structures to improve density and speed as well as continuing improvements to finFET processes.
finFET
Image sensors shrink at IEDM
This year’s IEDM features a number of papers that seek to drive down the size and boost the performance of image sensors.
IEDM 2021 publishes course schedule
Aiming for a primarily physical event in the fall, organisers of the 2021 IEDM have published the tutorial and short-core schedule.
TSMC spins outs processes for automotive and RF
TSMC is developing processes for high-end automotive and RF based off its N5 and N7 families.
Chipmaking’s new environment presented at IEDM
Imec's senior vice president of CMOS outlined future directions for the technology over the coming decade.
TSMC fills in sub-nodes as EUV gains ground
TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process.
Nanometer scaling puts focus on power at VLSI in June
Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
GlobalFoundries takes aim at TSMC’s customers in patent action
GlobalFoundries is calling for imports of chips fabbed by TSMC into the US and Germany in multiple actions based on a list of 16 patents.
Graphcore licenses ESD protection from Sofics
Graphcore has licensed IP from Belgium-based Sofics to protect its Colossus GC2 processors from ESD.
GlobalFoundries stops 7nm work to focus on existing processes
GlobalFoundries has decided to put development of its 7nm process on the backburner and focus on its existing finFET and FD-SOI processes.