Nanometer scaling puts focus on power at VLSI in June
Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
finFET
GlobalFoundries takes aim at TSMC’s customers in patent action
GlobalFoundries is calling for imports of chips fabbed by TSMC into the US and Germany in multiple actions based on a list of 16 patents.
Graphcore licenses ESD protection from Sofics
Graphcore has licensed IP from Belgium-based Sofics to protect its Colossus GC2 processors from ESD.
GlobalFoundries stops 7nm work to focus on existing processes
GlobalFoundries has decided to put development of its 7nm process on the backburner and focus on its existing finFET and FD-SOI processes.
Node-variant FinFET tweaks try to improve cost, performance
Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.
Samsung couples EUV with DTCO for 7nm shrink
Samsung Electronics expects to increase savings on die area in the shift from its 10nm to 7nm node by applying both EUV for critical layers and several layout-focused process changes.
SAR-VCO combo tunes RF receiver power on 16nm
Researchers from the UC Berkeley and Intel teamed up to develop an energy-tuneable RF front-end on a digital finFET process with no need for analog process options.
Mixed-signal circuits push scaled CMOS at VLSI
The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.
7nm process with EUV to feature at VLSI
Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
Cadence tunes Virtuoso for 5nm and SIP
Cadence Design Systems has made enhancements to its Virtuoso mixed-signal layout tool at both the system-level and nanometer-design levels for its 18.1 release.
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