ESL

August 19, 2019
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

Take advantage of the automated refactoring of design and verification code

Refactoring saves time and resuources by converting code to a common format and eliminates redundancies to make it more readable and maintainable.
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April 2, 2019

High-level synthesis for AI: Part Two

How Chips&Media used HLS on the development of a computer vision IP block.
March 26, 2019

High-level synthesis for AI: Part One

The computational and algorithmic demands made by computer vision systems highlight HLS' value for AI system development.
March 15, 2019

Enabling the move to a system-centric view

Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.
October 3, 2018
Allen Watson of Synopsys

An open-source framework for greater flexibility in machine-learning development

Exchange frameworks are emerging to make it easier for neural-network developers to swap between development environments.
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September 8, 2017

How HLS is giving shape to glasses-free 3DTV

High level synthesis (HLS) was adopted to realize innovative display IP as developed by a small core engineering team.
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May 8, 2017
Dr Walden Rhines is Chairman and CEO of Mentor - A Siemens Business

The Wally Rhines interview – Part One: Mentor as a Siemens business

Our extended fireside chat with Mentor Chairman and CEO Wally Rhines begins by canvassing his thoughts now the Siemens deal is done.
March 15, 2017
DVCon China takes place at the Parkyard Hotel, Shanghai on April 19th.

DVCon China launches this April in Shanghai

DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).
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June 1, 2016
How Google and Qualcomm use HLS and HLV

How Google and Qualcomm exploit real world HLS and HLV

By taking a pragmatic approach, the two technology giants have comfortably adopted high-level synthesis and verification - and have shared their experiences.
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May 23, 2016
Road signs used to train IDSIA neural network

Bit width tweaks point way to practical deep learning

In both data centers and automobiles deep learning is taking hold. But it is a technique that challenges conventional microprocessors, leading system designers to look at alternative architectures for acceleration.

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