Accellera

DVCon Europe has announced its two keynote presentations, focusing on energy-efficient high-performance computing and machine learning.

Accellera has formed a working group to look at the possibility of creating a standard for federated simulation.

DVCon Europe is expanding coverage into research on design verification for its 10th conference later this year.

Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.

The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.

Aside from the keynotes and technical papers, the networking at an event like DVCon Europe provides a way to keep open-source EDA on the road.

DVCon Europe's keynotes will examine verification issues in connected cars and 5G networks.

Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.

Variable lifetimes are an apparently basic but also tricky feature within the verification language.

DVCon Europe will be held as a live event in Munich in early December.