Accellera has formed a working group to look at extensions to SystemVerilog to improve support for mixed-signal designs.
The two best papers at the recent DVCon Europe underlined two of the issues that now face chip-implementation teams: efficient flows and reliability.
Accellera has published for public review version 0.1 of a standard designed to help pass clock-domain crossing information between EDA tools.
Accellera ’s board of directors has approved the version 2.1 of the Portable Test and Stimulus Standard.
DVCon Europe has announced its two keynote presentations, focusing on energy-efficient high-performance computing and machine learning.
Accellera has formed a working group to look at the possibility of creating a standard for federated simulation.
DVCon Europe is expanding coverage into research on design verification for its 10th conference later this year.
Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.
Aside from the keynotes and technical papers, the networking at an event like DVCon Europe provides a way to keep open-source EDA on the road.
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