DVCon Europe calls for papers for 2024 event
DVCon Europe is looking for papers to be presented at this year’s event in mid-October.
Accellera
Latest version of Verilog-AMS ready for release
The board of directors of Accellera Systems Initiative has approved the 2023 edition of the Verilog-AMS standard for release.
Accellera forms working group for mixed-signal interfaces
Accellera has formed a working group to look at extensions to SystemVerilog to improve support for mixed-signal designs.
Flow stability and chip reliability top the papers at DVCon Europe
The two best papers at the recent DVCon Europe underlined two of the issues that now face chip-implementation teams: efficient flows and reliability.
Accellera publishes draft of CDC standard
Accellera has published for public review version 0.1 of a standard designed to help pass clock-domain crossing information between EDA tools.
Accellera updates portable stimulus standard
Accellera ’s board of directors has approved the version 2.1 of the Portable Test and Stimulus Standard.
HPC and AI provide keynote focus at DVCon Europe
DVCon Europe has announced its two keynote presentations, focusing on energy-efficient high-performance computing and machine learning.
Accellera group formed to work on federated simulation
Accellera has formed a working group to look at the possibility of creating a standard for federated simulation.
DVCon Europe adds research track
DVCon Europe is expanding coverage into research on design verification for its 10th conference later this year.
Accellera forms CDC working group and takes security standard to IEEE
Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.