Accellera

March 13, 2024

DVCon Europe calls for papers for 2024 event

DVCon Europe is looking for papers to be presented at this year’s event in mid-October.
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March 4, 2024

Latest version of Verilog-AMS ready for release

The board of directors of Accellera Systems Initiative has approved the 2023 edition of the Verilog-AMS standard for release.
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February 8, 2024

Accellera forms working group for mixed-signal interfaces

Accellera has formed a working group to look at extensions to SystemVerilog to improve support for mixed-signal designs.
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December 27, 2023

Flow stability and chip reliability top the papers at DVCon Europe

The two best papers at the recent DVCon Europe underlined two of the issues that now face chip-implementation teams: efficient flows and reliability.
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October 31, 2023

Accellera publishes draft of CDC standard

Accellera has published for public review version 0.1 of a standard designed to help pass clock-domain crossing information between EDA tools.
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October 16, 2023

Accellera updates portable stimulus standard

Accellera ’s board of directors has approved the version 2.1 of the Portable Test and Stimulus Standard.
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September 6, 2023

HPC and AI provide keynote focus at DVCon Europe

DVCon Europe has announced its two keynote presentations, focusing on energy-efficient high-performance computing and machine learning.
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August 22, 2023

Accellera group formed to work on federated simulation

Accellera has formed a working group to look at the possibility of creating a standard for federated simulation.
April 17, 2023

DVCon Europe adds research track

DVCon Europe is expanding coverage into research on design verification for its 10th conference later this year.
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January 18, 2023

Accellera forms CDC working group and takes security standard to IEEE

Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
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