Accellera forms CDC working group and takes security standard to IEEE
Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
Accellera
DVCon Europe best paper speeds up memory-controller tests
The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.
DVCon Europe looks to network effects
Aside from the keynotes and technical papers, the networking at an event like DVCon Europe provides a way to keep open-source EDA on the road.
DVCon Europe keynotes focus on connectivity
DVCon Europe's keynotes will examine verification issues in connected cars and 5G networks.
Accellera attempts to standardize CDC data
Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.
Navigate variables and lifetimes in SystemVerilog
Variable lifetimes are an apparently basic but also tricky feature within the verification language.
DVCon Europe returns to live format
DVCon Europe will be held as a live event in Munich in early December.
DVCon events stick with virtual format and add speakers
DVCon US use a virtual platform for its event to be held in the spring and the organisers of the European event will employ a more sophisticated version of the virtual 3D space debuted last year.
Keynotes for DVCon Europe announced
DVCon Europe has announced its first two keynote speakers, who will cover the topics of AI and the role of virtualisation in ADAS design and implementation
Accellera approves IP security-documentation standard
Accellera has approved version 1.0 of the SA-EDI standard, intended to provide a consistent way of describing security concerns for IP cores.
PLATINUM SPONSORS
View All Sponsors