November 9, 2020
This year's IEDM will feature papers that exploit stacked nanoribbons to reduce CMOS footprint, graphene interconnects that support easier integration, and the variability prospects of 2D semiconductors.
July 21, 2020
DTCO and 3D integration will dominate scaling in the coming decade, TSMC chief scientist Philip Wong claimed in his keynote at DAC on Monday
July 2, 2019
There's still plenty of time to build a busy and profitable agenda for a visit to ES Design West and SEMICON West in San Francisco next week.
May 15, 2017
The 63rd IEDM has issued a call for papers for its conference in San Francisco in early December and has stuck with the later deadline introduced last year.
December 16, 2013
Industry-wide innovation is required to make scaling cost-effective at 7nm, says Qualcomm's VP of Technology. Time for a fat, cholesterol and MSG-free diet.
October 4, 2013
Research group CEA-Leti expects to have design kits ready for a 10nm FD-SOI process in June 2014
