3D integration technologies will blend says TSMC chief scientist
DTCO and 3D integration will dominate scaling in the coming decade, TSMC chief scientist Philip Wong claimed in his keynote at DAC on Monday
device scaling
The road to ES Design West: Location, location, location
There's still plenty of time to build a busy and profitable agenda for a visit to ES Design West and SEMICON West in San Francisco next week.
IEDM opts for later deadline on 63rd conference
The 63rd IEDM has issued a call for papers for its conference in San Francisco in early December and has stuck with the later deadline introduced last year.
Qualcomm’s take on preserving Moore’s Law economics
Industry-wide innovation is required to make scaling cost-effective at 7nm, says Qualcomm's VP of Technology. Time for a fat, cholesterol and MSG-free diet.
Design kit for 10nm FD-SOI due out next year
Research group CEA-Leti expects to have design kits ready for a 10nm FD-SOI process in June 2014
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