Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.
Samsung described at VLSI Symposia how it has used two further forms of stacking to increase flash capacity.
Imec showed at VLSI Symposia a process flow that can cut the gap between complementary transistors to less than 20nm.
TSMC will provide three different standard-cell libraries for its upcoming finFET-based 3nm process to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and circuit frequency.
The upcoming VLSI Symposia will feature a number of papers that show the ways in which novel approaches are going to be needed to continue scaling.
This year's IEDM will feature papers that exploit stacked nanoribbons to reduce CMOS footprint, graphene interconnects that support easier integration, and the variability prospects of 2D semiconductors.
DTCO and 3D integration will dominate scaling in the coming decade, TSMC chief scientist Philip Wong claimed in his keynote at DAC on Monday
There's still plenty of time to build a busy and profitable agenda for a visit to ES Design West and SEMICON West in San Francisco next week.
The 63rd IEDM has issued a call for papers for its conference in San Francisco in early December and has stuck with the later deadline introduced last year.
Industry-wide innovation is required to make scaling cost-effective at 7nm, says Qualcomm's VP of Technology. Time for a fat, cholesterol and MSG-free diet.
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