nanosheet


June 15, 2021

Imec cuts transistor gap to less than 20nm with forksheets

Imec showed at VLSI Symposia a process flow that can cut the gap between complementary transistors to less than 20nm.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
May 2, 2021

Alternative scaling approaches form VLSI 2021 technology highlights

The upcoming VLSI Symposia will feature a number of papers that show the ways in which novel approaches are going to be needed to continue scaling.
December 15, 2020

Chipmaking’s new environment presented at IEDM

Imec's senior vice president of CMOS outlined future directions for the technology over the coming decade.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
November 9, 2020

IEDM 2020 highlights transistor and interconnect advances

This year's IEDM will feature papers that exploit stacked nanoribbons to reduce CMOS footprint, graphene interconnects that support easier integration, and the variability prospects of 2D semiconductors.
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August 25, 2020

TSMC fills in sub-nodes as EUV gains ground

TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , , ,   |  Organizations: ,
June 16, 2020

Transistor stacks piled high at VLSI

As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.
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