Vertical integration is one of the major focus areas at the upcoming IEDM conference, both in terms of transistors and the multiple channels that will go into them.
Intel Foundry Services has signed a deal with Arm that will see the two companies work on a program of system and design-technology co-optimization.
At IEDM, TSMC is at the top of several papers that examine how 2D materials might be put into action as successors to silicon, alongside work from a variety of institutions on power integration and thermal management.
Three highlighted papers at IEDM, taking place in December, show the different approaches to the use of the vertical dimension to cut energy use and improve density.
Imec showed at VLSI Symposia a process flow that can cut the gap between complementary transistors to less than 20nm.
The upcoming VLSI Symposia will feature a number of papers that show the ways in which novel approaches are going to be needed to continue scaling.
Imec's senior vice president of CMOS outlined future directions for the technology over the coming decade.
This year's IEDM will feature papers that exploit stacked nanoribbons to reduce CMOS footprint, graphene interconnects that support easier integration, and the variability prospects of 2D semiconductors.
TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process.
As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.
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