nanosheet


June 16, 2020

Transistor stacks piled high at VLSI

As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , , , , ,   |  Organizations: ,

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