June 18, 2017
Accellera's Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
May 30, 2015
Clock-tree generation is coming under increased scrutiny because of its role in dynamic power consumption and problems caused by on-chip PVT variation.
May 28, 2015
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
July 23, 2014
The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.
July 15, 2014
Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.
July 13, 2014
Dynamic voltage and frequency scaling is effective for low-power VLSI design. Body or back bias can provide additional control over leakage and performance.
June 22, 2014
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
May 29, 2014
By taking the circuit supply voltage close to that of the threshold voltage or even below, it is possible to optimize low-power VLSI design. But there are pitfalls.
May 29, 2014
A static-analysis tool that checks for errors in HDL code, lint is becoming an increasingly important addition to simulation for RTL and SoC signoff.
May 28, 2014
As designs get larger and stress the ability of simulation to exercise an SoC, formal techniques have become essential parts of design and verification.