EDA

June 6, 2024

Real Intent tool looks at paths to hardware vulnerability

Real Intent has developed a tool for identifying potential security issues in chip designs at the sign-off stage.
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May 29, 2024

IEDM call for papers looks for tomorrow’s semiconductors

The 70th annual IEDM is putting together its next conference under the theme under the theme “shaping tomorrow’s semiconductor technology”.
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May 13, 2024

Dense packaging focus for ECTC

This year’s ECTC, held at the end of May, will continue its focus on the role of packaging in keeping silicon scaling on track.
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May 2, 2024

VLSI to explore vertical device changes and 3nm finFET

The upcoming VLSI Symposium will examine progress in using backside contacts and 3D structures to improve density and speed as well as continuing improvements to finFET processes.
April 11, 2024

Early package assembly verification for faster, better results

Make it easier to capture issues in 2.5D and 3D designs with multiple chiplets and emerging challenges with this 'shift left' approach.
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March 14, 2024

Two projects to deliver digital twins for software-defined vehicles

Arm is working with Cadence and Siemens on separate projects to support its plans in the SDV space.
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March 13, 2024

DVCon Europe calls for papers for 2024 event

DVCon Europe is looking for papers to be presented at this year’s event in mid-October.
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March 4, 2024

Latest version of Verilog-AMS ready for release

The board of directors of Accellera Systems Initiative has approved the 2023 edition of the Verilog-AMS standard for release.
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February 22, 2024

Cadence to work on IP for Intel 18A

Cadence has agreed to work with Intel Foundry Services on IP and flows for the 18A process, which will include backside power delivery and nanosheet transistors.
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February 8, 2024

Accellera forms working group for mixed-signal interfaces

Accellera has formed a working group to look at extensions to SystemVerilog to improve support for mixed-signal designs.
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