EDA

March 27, 2020

Tackling IR drop and EM with a push-button via utlility

Traditional approaches to via insertion to meet reliability and yield at advanced nodes are giving way to necessary automation.
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March 24, 2020

Feed fake news to hardware hackers

Intel describes active countermeasures for physical attacks at CICC as part of a trend towards more adaptive IoT silicon.
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March 19, 2020

Deploying pre- and post-silicon verification and test for 5G designs

A flexible and still evolving range of 5G standards requires methodologies that can handle massive test.
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March 3, 2020

DVCon US 2020: Coronavirus program changes

DVCon US 2020 is to end a day early as a result of the COVID-19 coronavirus outbreak and released an updated agenda.
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February 28, 2020

Learn how Renesas uses SLEC to enhance its verification flows

A new technical article discusses Renesas' addition of SLEC to its SystemC and RTL flows and the improvements it achieved in time and coverage..
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February 27, 2020

DVCon US 2020 preview: Breker Verification Systems

Portable stimulus pioneer Breker will feature across the DVCon program also highlighting its work with RISC-V.
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February 26, 2020

DVCon US 2020 preview: ESD Alliance

The Electronic System Design Alliance will discuss the benefits it offers for design and verification, and has added Avery Design Systems.
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February 26, 2020

DVCon US 2020 preview: Verific

Tool development specialist Verific will demonstrate its parsers and their integration with INVIO APIs.
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February 24, 2020

DVCon US 2020 preview: Mentor

Mentor will have a very broad presence at DVCon across technologies such as HLS, formal verification, simulation and emulation.
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February 18, 2020

Accellera moves to working-group stage for functional-safety standard

Accellera has set up a working group with the aim of developing interoperability standards for functional safety.
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