EDA

September 14, 2020

Aprisa team to be doubled after Mentor purchase

Mentor, a Siemens business, plans to expand the team working on the Aprisa place-and-route tool following the purchase of Avatar Integrated Systems, announced in July.
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August 27, 2020

Cloud access to emulator helps AI processor start-up prove design, win funding

Small startup gets flexible cloud access to big iron to prove a novel processor architecture quickly.
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August 25, 2020

TSMC fills in sub-nodes as EUV gains ground

TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process.
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August 17, 2020

Cadence uses machine learning to trim constrained-random runtimes

Cadence has developed a stimulus optimizer based on neural networks to try to improve the runtime of constrained-random verification runs.
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July 31, 2020

Open-RAN puts more focus on emulation in testing programs

Recent developments have made Open-RAN look more attractive as a way of implementing 5G systems. This is helping to drive a shift-left in verification and test.
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July 23, 2020

Accellera IP security group expects standard by year end

The chair of Accellera’s IP security assurance working group expects the draft standard for hardening hardware core to be out by the end of the year.
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July 21, 2020

DAC Pavilion focuses on cloud-scaling issues

Talks in the Design-on-Cloud Pavilion at this year’s DAC demonstrated how the question over its usage is not so much whether design could or should migrate to the cloud but how to optimize cost and performance when it’s there.
July 21, 2020

3D integration technologies will blend says TSMC chief scientist

DTCO and 3D integration will dominate scaling in the coming decade, TSMC chief scientist Philip Wong claimed in his keynote at DAC on Monday
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July 21, 2020

Breker packages up apps for RISC-V, security and AI

Breker has added a number of specialized apps to its library that deal with the verification of RISC-V processors, secure enclaves, and machine-learning designs.
July 20, 2020

FastSPICE upgrade boosts nano-scale analog verification by up to 10X

Mentor adds Analog FastSPICE eXTreme innovations for designs facing increasing parasitic complexity and contact resistance challenges at cutting edge nodes.
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