DVCon Europe has announced its two keynote presentations, focusing on energy-efficient high-performance computing and machine learning.
Accellera has formed a working group to look at the possibility of creating a standard for federated simulation.
Just how much of the flow has already has 'shift left' benefit and what is fueling further progress.
Tessolve is bringing its Verification Futures conference to the US with an event scheduled for mid-September.
Backside power delivery could lead to improvements in chip density and more straightforward place-and-route phases according to work presented at this year’s VLSI Symposium.
The recent Verification Futures Europe conference looked at what AI, from decision trees to foundation models, could do to speed up RTL checks.
Calibre Design Enhancer moves physical verification checks and automated DRC-clean via and cell insertion into P&R
Three fast developing AI techniques underpin the efficiencies in the new Solido custom design and verification platform.
At the recent VLSI Symposium, Google vice president Parthasarathy Ranganathan described the importance of co-design and the software stack in its data-center designs.
Siemens has published a white paper that examines whether package designers need to adopt IC tools and design styles in the move from organic packages to 2.5DIC packages.
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