Sigasi has launched a software kit to provide inhouse tools builders and EDA vendors with a way to build in code-editing features.
The organizers of the 66th annual IEDM have decided to hold the December conference virtually.
Waferscale SSDs are among the future drive architectures being explored by Kioxia, according to a keynote delivered at VLSI Symposia.
Even experienced IC design houses must adopt innovative and emerging strategies to meet functional safety and other demands of ISO 26262 for automotive systems.
As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.
Real Intent has launched a DFT tool intended to relax the bottlenecks that occur as an SoC project moves into its final phase ahead of tapeout.
The IEEE plans to stage the 66th International Electron Device Meeting as a physical event in mid-December.
DVCon US is to repeat sessions online from today until the middle of August, with exclusive access to registered attendees through early June.
Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
A white paper details the parasitic extraction technology needed to help design high-performance RF SoCs.
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