EDA

March 14, 2024

Two projects to deliver digital twins for software-defined vehicles

Arm is working with Cadence and Siemens on separate projects to support its plans in the SDV space.
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March 13, 2024

DVCon Europe calls for papers for 2024 event

DVCon Europe is looking for papers to be presented at this year’s event in mid-October.
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March 4, 2024

Latest version of Verilog-AMS ready for release

The board of directors of Accellera Systems Initiative has approved the 2023 edition of the Verilog-AMS standard for release.
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February 22, 2024

Cadence to work on IP for Intel 18A

Cadence has agreed to work with Intel Foundry Services on IP and flows for the 18A process, which will include backside power delivery and nanosheet transistors.
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February 8, 2024

Accellera forms working group for mixed-signal interfaces

Accellera has formed a working group to look at extensions to SystemVerilog to improve support for mixed-signal designs.
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February 1, 2024

Future Facilities core drives Cadence thermal suite

Cadence has introduced a platform for performing thermal and thermal-stress analysis of subsystems, from 2.5D and 3DICs to PCBs and complete electronic assemblies.
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January 12, 2024

DVCon gears up for March in San Jose

Workshops on portable stimulus, functional safety, verification of RISC-V processors, and design with chiplets and large language models will feature at the upcoming 2024 DVCon US.
December 27, 2023

Flow stability and chip reliability top the papers at DVCon Europe

The two best papers at the recent DVCon Europe underlined two of the issues that now face chip-implementation teams: efficient flows and reliability.
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December 22, 2023

Sustainability work puts numbers on chipmaking production at IEDM

Shifting to low-carbon generation for electricity would do much to cut the carbon footprint of semiconductor processes according to work shown at this year’s IEDM.
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December 18, 2023

FD-SOI processes lead to double-decker monolithic 3D

At IEDM, CEA-Leti described a process that avoids the thermal problems of implementing CMOS transistors in the metal stack using monolithic integration.
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