EDA

January 19, 2020

Verific celebrates two decades of parser pre-eminence

The parser specialist has built a loyal fanbase across the electronics system design infrastructure with users now lining up to mark its 20th birthday.
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January 7, 2020

Siemens and Arm combine to extend digital twin further into SoC design

Partnership combines Siemens PAVE 360 digital twin with ARM IP, including dedicated automotive offerings, to speed and streamline design toward Level 5.
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December 18, 2019

On-demand DRC within P&R cuts closure time in half for MaxLinear

Case study describes how RF/AMS specialist used Calibre RealTime Digital within its flow for a high-end DSP SoC.
December 18, 2019

Capacitive link to power cheap wireless tags

Imec, TNO, and Cartamundi have developed a low-cost way of letting tags communicate with embedded devices wirelessly by using a capacitive touchscreen.
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December 17, 2019

Automating the pain out of clock domain crossing verification

A new CDC methodology uses automation and data hooks to improve a notoriously lengthy and tricky task - verifying synchronizers.
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December 16, 2019

Mentor delivers eMRAM test for ARM/Samsung FDSOI at 28nm

Tessent test suite targets automotive, AI and IoT projects that need embedded non-volatile memory.
December 10, 2019

Breker adds automated system integration test generation for RISC-V

App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.
December 4, 2019

Cadence to acquire AWR from National Instruments

Cadence Design Systems has agreed to buy the AWR RF-design company from its current owner National Instruments for approximately $160m.
November 19, 2019

2020 VLSI Symposia to look at the next 40 years

Having provided a forum for describing the progress of process technology and circuit design for four decades, the organizers of the 2020 Symposia on VLSI Technology & Circuits are asking presenters to look at the coming 40 years.
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November 12, 2019

Mentor cuts scan time in package of test measures for automotive designs

Aimed at automotive designs, Mentor has developed a BIST technology that the company claims can speed up the process ten-fold by making more of each scan cycle.
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