The automotive market faces challenges that make it a prime candidate for the greater use of high-level synthesis on designs with AI and ML content.
A new whitepaper describes some of the techniques you can use to get the most out of cloud-based DRC with Calibre.
Accellera has set up a public repository for the source code and other supplemental material needed for its standards.
Reset domain crossing is another area where rising SoC complexity and IP reuse is causing an increase in reliability and safety challenges.
Konica Minolta describes how it has constructed a C++ signoff flow that mitigates code ambiguity, manual analysis and other inefficiencies.
Coventor has updated its SEMulator virtual-fab tool and added the ability to tune process windows based on simulation results.
The Bangalore conference has issued a last-minute call for panel proposals as technical paper submissions for the US edition get set to open next week.
A new paper describes an alternative to increasingly inefficient manual ESD verification that reduces risks of respins and missed delivery deadlines.
There's still plenty of time to build a busy and profitable agenda for a visit to ES Design West and SEMICON West in San Francisco next week.
The verification IP is the first to become commercially available for the bus interface backed by companies such as AMD, Google, IBM, Micron and Xilinx.
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