June 6, 2024
Real Intent has developed a tool for identifying potential security issues in chip designs at the sign-off stage.
May 29, 2024
The 70th annual IEDM is putting together its next conference under the theme under the theme “shaping tomorrow’s semiconductor technology”.
May 13, 2024
This year’s ECTC, held at the end of May, will continue its focus on the role of packaging in keeping silicon scaling on track.
May 2, 2024
The upcoming VLSI Symposium will examine progress in using backside contacts and 3D structures to improve density and speed as well as continuing improvements to finFET processes.
April 11, 2024
Make it easier to capture issues in 2.5D and 3D designs with multiple chiplets and emerging challenges with this 'shift left' approach.
March 14, 2024
Arm is working with Cadence and Siemens on separate projects to support its plans in the SDV space.
March 13, 2024
DVCon Europe is looking for papers to be presented at this year’s event in mid-October.
March 4, 2024
The board of directors of Accellera Systems Initiative has approved the 2023 edition of the Verilog-AMS standard for release.
February 22, 2024
Cadence has agreed to work with Intel Foundry Services on IP and flows for the 18A process, which will include backside power delivery and nanosheet transistors.
February 8, 2024
Accellera has formed a working group to look at extensions to SystemVerilog to improve support for mixed-signal designs.