EDA's lower profile during the US-China semiconductor face-off could be coming to an end.
The formal apps start-up has built strong positions in automotive and RISC-V and will strengthen Siemens in competition with Cadence.
The Accellera board has approved version 2.0 of the Portable Test and Stimulus Standard.
The vendor has reworked its website and discussed more about its strategy going forward, following its rebranding from Mentor.
Accellera has published the version 1.0 draft of the proposed Security Annotation for Electronic Design Integration standard.
Cadence Design Systems has designed a new custom processor for the Z2 emulator and employed Xiliinx UltraScale+ for the prototyping platform.
Imperas Software has released a free instruction set simulator that covers the OpenHW Group's implementations of the RISC-V processor architecture.
Siemens Digital Industries Software has launched the latest generation of its Veloce hardware-assisted verification systems with a product line that encompasses silicon virtual platform, hardware emulation, and prototyping support.
The best paper awards at this month's DVCon highlighted techniques to streamline verification. The European version in the meantime is looking for paper submissions.
IRPS will use a virtual format for its March conference and will take in the reliability of emerging as well as more established technologies.
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