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May 13, 2024

Dense packaging focus for ECTC

This year’s ECTC, held at the end of May, will continue its focus on the role of packaging in keeping silicon scaling on track.
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November 22, 2023

Arm gives Helium to low-end Cortex-M core

Arm has added machine-learning extensions and pointer-security instructions to its latest Cortex-M series core.
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November 17, 2023

Siemens takes automotive digital twin to the AWS cloud

Siemens has made its PAVE360 automotive digital-twin software available on AWS, with the ability to access fast Arm models on the same cloud.
October 31, 2023

Imperas builds model of Tenstorrent AI core

Imperas Software has worked with AI specialist Tenstorrent to create and distribute a model of the Ascalon processor core.
October 6, 2023

Fast instruction simulator expands to Arm

MachineWare has expanded its portfolio of high-speed instruction-set simulators to the Arm Cortex-A and -M architectures.
October 3, 2023

Siemens and CEA link up on AI-assisted digital twins

Siemens and CEA-List have signed a deal under which the two organisations will research the combination of digital-twin and AI.
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December 1, 2022

Siemens aims to simplify compliance for Linux medical devices

New Quality Package focuses on safety and cybersecurity compliance with EU and US medical device standards.
August 31, 2022

Intel and partners join for RISC-V development push

Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
June 30, 2022

Siemens and Nvidia aim to bring more virtual reality to digital twins

Siemens and Nvidia have agreed to work more closely together to drive the development of higher-fidelity digital twins.
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June 28, 2022

Aachen spinout claims fastest RISC-V simulator

MachineWare claims it can reach 2GHz throughput with instruction-set simulator for RISC-V processors.

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