Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
Siemens and Nvidia have agreed to work more closely together to drive the development of higher-fidelity digital twins.
MachineWare claims it can reach 2GHz throughput with instruction-set simulator for RISC-V processors.
Siemens has expanded its Nucleus ReadyStart program to the RISC-V architecture.
A Siemens Tessent white papers examines the role of safety islands in advanced automotive systems.
Vulnerabilities in connected healthcare products have led medical requlators to issue further security recommendations for their design and maintenance.
Xilinx has reworked its Versal FPGA for edge-AI applications.
Determining which embedded technique to adopt is more than just a question of what cores the system has.
Arm aims to introduce a novel security model in its upcoming v9 architecture along with further extensions for AI.
Imperas Software has released a free instruction set simulator that covers the OpenHW Group's implementations of the RISC-V processor architecture.
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