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This year’s ECTC, held at the end of May, will continue its focus on the role of packaging in keeping silicon scaling on track.

Arm has added machine-learning extensions and pointer-security instructions to its latest Cortex-M series core.

Siemens has made its PAVE360 automotive digital-twin software available on AWS, with the ability to access fast Arm models on the same cloud.

Imperas Software has worked with AI specialist Tenstorrent to create and distribute a model of the Ascalon processor core.

MachineWare has expanded its portfolio of high-speed instruction-set simulators to the Arm Cortex-A and -M architectures.

Siemens and CEA-List have signed a deal under which the two organisations will research the combination of digital-twin and AI.

New Quality Package focuses on safety and cybersecurity compliance with EU and US medical device standards.

Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.

Siemens and Nvidia have agreed to work more closely together to drive the development of higher-fidelity digital twins.

MachineWare claims it can reach 2GHz throughput with instruction-set simulator for RISC-V processors.