Embedded

February 21, 2019

EmbeddedWorld 2019 preview: Mentor

The company will share a stand at EmbeddedWorld in Nuremberg with its sister Siemens division Polarion and has seven papers across the technical program.
February 21, 2019

Mentor Embedded Linux launch targets enterprise-class gap

The suite is based on Debian and aims to offer the performance and configurability needed for robust and scaleable enterprise-class applications in medical, industrial, aerospace and defense markets.
February 8, 2019

Taking an IoT edge design from proof-of-concept to prototype

A new paper describes a case study for a pressure-sensing IoT application based on the ARM DesignStart platform and Mentor IoT tool flow.
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January 22, 2019

HPC futures report puts acceleration first

A report put together by Europe's HiPEAC high-performance computing research network argues computing is at an architectural turning point
January 7, 2019

Ceva extends control-oriented DSP

Ceva has followed its IoT-oriented Ceva-X series of processor cores with a more powerful family that is designed to handle control and signal-processing algorithms using the same pipeline.
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December 6, 2018

Microchip opts for RISC-V cores in SoC FPGA

Microsemi has put multiple RISC-V cores into a new generation of SoC FPGAs, intended for embedded systems that need to run Linux.
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October 31, 2018

Cadence adds deep-learning support to audio DSP

Cadence has added direct support for neural networks to the latest iteration of its DSP cores aimed at audio systems.
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September 26, 2018

DVCon Europe keynotes take in digital twin and IoT concepts

Two keynote speakers have been announced for DVCon Europe 2018, which takes place next month.
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September 24, 2018

Module strategies try to streamline IoT trials

Suppliers to the embedded industry see modules and readymade software as being key to getting IoT projects off the ground.
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September 19, 2018

Cadence culls zeroes for faster neural throughput

Cadence has launched an AI processor using an designed to take advantage of the sparse structure of typical deep neural networks.
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