Alps Alpine composes capacitance IC with Symphony
The company says the mixed-signal platform enabled a 5X improvement in verification productivity.
Siemens EDA
Achieving functional coverage of multi-language designs
There is no comprehensive standard yet for functional coverage across designs using SystemC, TLM, UVM and SystemVerilog, but there are options using UVM Connect.
Siemens harnesses machine learning for more comprehensive verification
As first silicon success declines, new software aims to provide a more holistic view of coverage data from multiple sources.
Identifying AI opportunities in PCB design
The key to exploiting AI is being clear about where its family of technologies can help to improve and democratize design.
Siemens aims to simplify compliance for Linux medical devices
New Quality Package focuses on safety and cybersecurity compliance with EU and US medical device standards.
Chipletz pushes packaging design for AI, HPC and immersive use-cases
The Austin-based start-up used Siemens EDA software to deploy a cutting-edge Smart Substrate based on advanced packaging technology.
Siemens automates test to handle multi-die 2.5D, 3D and 5.5D architectures
Tessent Multi-die extends the capabilities of the DFT suite in line with new standards intended to enable widespread adoption of interposer and stacked die strategies.
Module verification demands integrated DRC and LVS
The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
Use equivalence checking to retarget obsolete FPGA designs
Equivalence checking supports the efficient reuse of designs that reside on out-of-date silicon but remain valid in their own right.
Parasitic extraction challenges intensify for 5G
5G IC designs have needed aggressive innovation across many elements and more use of FD-SOI that both pose parasitic extraction challenges.
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