April 25, 2023
The company says the mixed-signal platform enabled a 5X improvement in verification productivity.
April 17, 2023
There is no comprehensive standard yet for functional coverage across designs using SystemC, TLM, UVM and SystemVerilog, but there are options using UVM Connect.
January 31, 2023
As first silicon success declines, new software aims to provide a more holistic view of coverage data from multiple sources.
December 1, 2022
The key to exploiting AI is being clear about where its family of technologies can help to improve and democratize design.
December 1, 2022
New Quality Package focuses on safety and cybersecurity compliance with EU and US medical device standards.
November 23, 2022
The Austin-based start-up used Siemens EDA software to deploy a cutting-edge Smart Substrate based on advanced packaging technology.
September 27, 2022
Tessent Multi-die extends the capabilities of the DFT suite in line with new standards intended to enable widespread adoption of interposer and stacked die strategies.
September 8, 2022
The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
September 8, 2022
Equivalence checking supports the efficient reuse of designs that reside on out-of-date silicon but remain valid in their own right.
September 5, 2022
5G IC designs have needed aggressive innovation across many elements and more use of FD-SOI that both pose parasitic extraction challenges.