The Austin-based start-up used Siemens EDA software to deploy a cutting-edge Smart Substrate based on advanced packaging technology.
Tessent Multi-die extends the capabilities of the DFT suite in line with new standards intended to enable widespread adoption of interposer and stacked die strategies.
The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
Equivalence checking supports the efficient reuse of designs that reside on out-of-date silicon but remain valid in their own right.
5G IC designs have needed aggressive innovation across many elements and more use of FD-SOI that both pose parasitic extraction challenges.
Learn how one of the leading tool vendors addresses the security of its products and customer data through a ground-up cybersecurity strategy.
Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
Siemens has launched Calibre DRC engines that make it easier to perform useful checks early in the layout process.
Siemens EDA has launched a second version of its Symphony simulation environment designed to support quicker debug cycles.
Aki Fujimura of mask specialist D2S sees curved shapes as key to improving die yield and performance but it needs EDA support.
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