Mentor

June 6, 2019

Calibre scales to 4000 nodes for faster sign off in the cloud

AMD used Calibre with optimisations implemented for cloud support to slash runtimes on high-end server processor designs.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: , , ,
June 4, 2019

Two-year surge is no blip – Wally Rhines

Wally Rhines, CEO Emeritus of Mentor, a Siemens business, delivered a bullish prognosis for the semiconductor and EDA sectors in a talk at the beginning of the Design Automation Conference in Las Vegas this week.
June 4, 2019

DAC to colocate with Semicon West next year

SEMI and the Design Automation Conference (DAC) have agreed to schedule the the US event for EDA alongside Semicon West in 2020 and 2021.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations: , , ,
May 27, 2019

Automotive complexity drives DFT to the RTL

Design-for-test can no longer be left until the gate level for increasingly sensitive designs aimed at newer processes.
Article  |  Topics: Blog - EDA, - Tested Component to System  |  Tags: , , , ,   |  Organizations:
May 23, 2019

AI and ML fuel Catapult and Calibre updates

Mentor takes the wraps off new machine learning fueled features in its HLS and physical design families ahead of DAC 2019.
May 20, 2019

How PAVE360 helps set a path toward the automotive digital twin

Siemens' new automotive platform commercializes and illustrates the company's ongoing integration of Mentor EDA products within its digital twin concept.
Article  |  Topics: Blog - EDA, Electrical Design  |  Tags: , , , ,   |  Organizations: ,
May 20, 2019

DAC 2019 preview: Mentor

Mentor is active across the program and its main and Verification Academy booths within the exhibition in Las Vegas.
April 26, 2019

The evolution of the digital twin

A digital twin is now more than just a virtual copy of a product. For Siemens, it is a multilayered concept powering a 'boundary-free innovation platform'.
Article  |  Topics: Commentary, Conferences, Blog - EDA, PCB  |  Tags: , , , ,   |  Organizations: , ,
April 18, 2019

User2User Silicon Valley is two weeks away

Mentor's technical conference will take place on May 2 at the Santa Clara Marriott and feature more than 45 user and vendor presentations.
April 16, 2019

Boost your DFT efficiency for AI silicon design

Three hierarchical DFT strategies help cut time-to-market for large AI chips by exploiting regularity and addressing test at the RTL.
Article  |  Topics: Blog Topics, Tested Component to System  |  Tags: , , , , , ,   |  Organizations:

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