Mentor

June 23, 2020

Mentor to bring SoC debug and instrumentation into the portfolio

Siemens has agreed to acquire UK-based debug and on-chip instrumentation startup UltraSoC and will fold the operation into Mentor’s Tessent test-software product line.
Article  |  Topics: Blog - IP  |  Tags: , , , , ,   |  Organizations: ,
June 23, 2020

How to draw upon Mentor-Microsoft integration for embedded IoT

The combination of Embedded Linux and Azure is supported by services and technologies that speed the delivery and deployment of MCU-based projects.
June 18, 2020

How Ambarella met the demands of automotive DFT

Even experienced IC design houses must adopt innovative and emerging strategies to meet functional safety and other demands of ISO 26262 for automotive systems.
June 17, 2020

Siemens raises Capital to full E/E design level

Capital has been grown from a wire harness suite to a full electrical/electronic platform with integration for digital twin strategies.
June 15, 2020

EDA in the cloud boosts DRC iterations for AMD

AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.
Article  |  Topics: Blog Topics  |  Tags: , , , , , , , , ,   |  Organizations: , , ,
May 28, 2020

Coverage without tears

A technical paper originally presented at DVCon USA 2020 simplifies the creation of coverage strategies using manual, automated and verification IP components.
Article  |  Topics: Conferences, Verification  |  Tags: , , , , ,   |  Organizations: ,
May 22, 2020

Parasitic extraction to guide capacitor usage in RF SoCs

A white paper details the parasitic extraction technology needed to help design high-performance RF SoCs.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
May 15, 2020

Coronavirus Resources: Mentor

Live and on-demand videos as well as You Tube 'tips and techniques' clips form part of a wide 'work at home' support package from Mentor.
April 23, 2020

Balancing PPA as machine learning moves to the edge

High-level synthesis is playing another important role in the matching of AI algorithms to necessarily application-specific designs.
April 22, 2020

Analyzing common resistance to deliver design reliability

Automated resistance checks mitigate the increasing complexity involved when analyzing voltage drop, ESD and noise, particularly for analog-heavy designs.

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