Traditional approaches to via insertion to meet reliability and yield at advanced nodes are giving way to necessary automation.
A flexible and still evolving range of 5G standards requires methodologies that can handle massive test.
A new technical article discusses Renesas' addition of SLEC to its SystemC and RTL flows and the improvements it achieved in time and coverage..
Mentor will have a very broad presence at DVCon across technologies such as HLS, formal verification, simulation and emulation.
Six papers, a dedicated automotive sessions and demos including the use of the Nucleus for RISC-V are among highlights in Mentor's Embedded World agenda.
Mythic will use the Mentor tools for its analog-targeted intelligence processing units.
Deadlock is hard to detect even though there are formal strategies for doing so. But wouldn't it be better if you could automate that work? Now you can.
By analyzing topology during the schematic design phase, you can detect latch-up issues before post-layout ERCs and avoid late stage revisions.
Partnership combines Siemens PAVE 360 digital twin with ARM IP, including dedicated automotive offerings, to speed and streamline design toward Level 5.
Case study describes how RF/AMS specialist used Calibre RealTime Digital within its flow for a high-end DSP SoC.
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