Mentor

March 27, 2020

Tackling IR drop and EM with a push-button via utlility

Traditional approaches to via insertion to meet reliability and yield at advanced nodes are giving way to necessary automation.
Article  |  Topics: Digital/analog implementation, Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
March 19, 2020

Deploying pre- and post-silicon verification and test for 5G designs

A flexible and still evolving range of 5G standards requires methodologies that can handle massive test.
February 28, 2020

Learn how Renesas uses SLEC to enhance its verification flows

A new technical article discusses Renesas' addition of SLEC to its SystemC and RTL flows and the improvements it achieved in time and coverage..
Article  |  Topics: Blog - EDA, - HLS  |  Tags: , , ,   |  Organizations: ,
February 24, 2020

DVCon US 2020 preview: Mentor

Mentor will have a very broad presence at DVCon across technologies such as HLS, formal verification, simulation and emulation.
Article  |  Topics: Blog - EDA, - HLS, Next Generation Design, Standards, Verification  |  Tags:   |  Organizations: ,
February 19, 2020

Embedded World 2020 preview: Mentor

Six papers, a dedicated automotive sessions and demos including the use of the Nucleus for RISC-V are among highlights in Mentor's Embedded World agenda.
February 12, 2020

AI processor company opts for Analog FASTSPICE and Symphony

Mythic will use the Mentor tools for its analog-targeted intelligence processing units.
January 29, 2020

Toward more efficient formal strategies for deadlock

Deadlock is hard to detect even though there are formal strategies for doing so. But wouldn't it be better if you could automate that work? Now you can.
Article  |  Topics: Blog Topics, Verification  |  Tags: , , , , , ,   |  Organizations:
January 28, 2020

Earlier latch-up prevention with topology-based analysis

By analyzing topology during the schematic design phase, you can detect latch-up issues before post-layout ERCs and avoid late stage revisions.
January 7, 2020

Siemens and Arm combine to extend digital twin further into SoC design

Partnership combines Siemens PAVE 360 digital twin with ARM IP, including dedicated automotive offerings, to speed and streamline design toward Level 5.
Article  |  Topics: Digital Twin, Blog - EDA, IP, PCB  |  Tags: , , , ,   |  Organizations: , ,
December 18, 2019

On-demand DRC within P&R cuts closure time in half for MaxLinear

Case study describes how RF/AMS specialist used Calibre RealTime Digital within its flow for a high-end DSP SoC.

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