A Mentor-Samsung collaboration cuts the need for model-based analysis and speeds analysis runtime by as much as 20X.
There's still plenty of time to build a busy and profitable agenda for a visit to ES Design West and SEMICON West in San Francisco next week.
Mentor takes the wraps off new machine learning fueled features in its HLS and physical design families ahead of DAC 2019.
Innovation and advances in EUV and OPC lead Mentor's offerings at SPIE in San Jose later this month.
The major West Coast technical conference for lithography is just two weeks away and offers a packed agenda.
The Calibre vendor will have a strong technical presence at the leading lithography conference taking place in late February in San Jose.
IMEC and Cadence have taped out a test chip intended to explore key lithography and metal-interconnect issues that will face users of the forthcoming 5nm process node.
Following Mentor's acquisition of Tanner EDA, management expect the integration will help with a drive into IoT applications and systems that need to go beyond standard IC lithography.
Is the industry ready to go beyond 10nm when it comes to lithography? Lithography researcher Professor David Pan sees design and process co-operation as the key approach.
Are we torn between evolution and revolution? Mentor Graphics' Joe Sawicki discusses how pattern matching already in fabs could move up and radically alter the design flow.
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