5nm

TSMC has certified the Aprisa place-and-route software from Siemens Digital Industries Software for the N5 and N4 process technologies.

All engines in the place-and-route software have been boosted with cuts to runtime and memory footprint.

TSMC is developing processes for high-end automotive and RF based off its N5 and N7 families.

TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process.

The organizers of the 66th annual IEDM have decided to hold the December conference virtually.

As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.

AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.

Moortec has reworked its thermal-sensing core design to allow for finer-grained use on SoCs being designed for the 5nm node.

The IEEE plans to stage the 66th International Electron Device Meeting as a physical event in mid-December.

There's still plenty of time to build a busy and profitable agenda for a visit to ES Design West and SEMICON West in San Francisco next week.