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IJTAG standards progress - featured image

Refreshing the IEEE 1687 IJTAG family for today’s designs

Learn more about how the IJTAG family and associated standards are being enhanced for current challenges.

Guides

  • Monolithic 3DIC for SoC

    EDA - Technologies

    Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.

  • Interconnect resistance

    EDA - Techniques

    A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.

  • Real-number or wreal modeling

    EDA - Techniques

    Real-valued modelling provides a way of speeding up the simulation of SoCs with significant analog content through the use of discrete-event solvers.

Expert Insights

Matt Walsh

Welcome to the part model era

Matthew Welsh, Siemens DIS

Standards-based digital threads will revolutionize design through part models that deliver trust, traceability and context across components.

Lauro Rizzatti

Shift left to tackle key O-RAN verification challenges

O-RAN compatible Radio Unit (O-RU) and Distributed Unit (O-DU) verification no longer needs to wait until the post-silicon stage.

Nebabie Kebebew

How to migrate SoC design to the cloud

Moving part of all of a design flow to the cloud involves careful preparation and evaluation as there is no 'one-size-fits-all'.

EDA

  1. 3D IC workflow democratization
    Expert Insight Give the people what they want: toward making 3D IC mainstream

    Learn more about the five interconnected workflows that are democratizing next generation design in the emerging chiplet age.

  2. Article Putting it all together to accelerate 3D IC design
  3. Expert Insight Reliability verification simplified for multi-power domain designs

PCB

  1. Stephen Chavez is a senior printed circuit engineer and a Senior Product Marketing Manager at Siemens EDA. Stephen is an IPC Certified Master Instructor Trainer (MIT) for PCB design, an IPC Certified Advanced PCB Designer (CID+), and a Certified Printed Circuit Designer (CPCD). He is chairman of the Printed Circuit Engineering Association (PCEA)
    Expert Insight A three-phase strategy to master the supply chain tsunami

    Knowledge, intelligence and optimization are key to managing the logistical disruption seen since the Covid-19 outbreak.

  2. Expert Insight May the Cloud be with you
  3. Article The five pillars of digital transformation for electronics system design

IP

  1. Formal verification for SystemC thumbnail
    Article Formal verification for SystemC/C++ designs

    Automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis. This tutorial, first presented at DVCon Europe explores how these formal techniques can be deployed and provides real-world examples.

  2. Article Resolving IP cell-name conflicts peacefully
  3. Article How to use runtime monitoring for automotive functional safety

Embedded

  1. Jeff Hancock is a Senior Product Manager in the Embedded Platform Technology Business Unit of Mentor, A Siemens Business. He oversees the Nucleus and Mentor Embedded Hypervisor runtime product lines, as well as associated middleware and professional services.
    Expert Insight Keeping up with rapid innovation in cockpit domain controllers

    Automotive cockpit design is being driven forward by prevailing trends in the wider market.

  2. Expert Insight Use digitalization to mitigate the automotive MCU shortage
  3. Expert Insight Implementing medical device security for optimal outcomes

Briefing

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