Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
Mentor is rolling out an comprehensive cloud-based design infrastructure feeding into digital twin strategies.
More commonly associated with SystemVerilog, IDEs can also greatly help users of the popular HDL for FPGA, mil/aero and other designs.
Virtualization is becoming ever more common during the Covid-19 outbreak, even for complex technologies like emulation, and showing its strengths.
Article Keep chip designs on the level with CMP simulation and dummy fill optimization
This case study shows how rising CMP simulation quality can be leveraged to detect the position and type of planarity hotspots before manufacture and verify the planarity of a layout.
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Article The necessity and benefits of ECAD-MCAD collaboration for PCB design
Collaboration across the electrical and mechanical domains leverages more tightly integrated and highly featured tools with richer data formats for greater accuracy and shorter time-to-market.
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Article Implementing high performance, low power Bluetooth Low Energy interfaces in SoCs
A look at the complexiites of implementing a Bluetooth Low Eenergy interface in an SoC.
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Expert Insight Delivering on security for Linux-based medical devices
How should you address the monitoring and resource challenges in maintaining security for Linux devices.
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