Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
How an integrated design environment can help you overcome complexities within the Universal Verification Methodology and manage the size of the libraries within it.
How Siemens PAVE 360 platform leverages emulation to deliver the exhaustive test required for the incoming generation of autonomous vehicles.
How to implement self-test across the four main areas where embedded systems can fail.
Article Managing code coverage to achieve verification closure in low-power SoCs
A look at some of the key techniques needed to ensue good code coverage during the verification of low-power SoC designs.
- Expert Insight Improve your LVS debug productivity
- Expert Insight Accelerating the adoption of portable stimulus
Article The necessity and benefits of ECAD-MCAD collaboration for PCB design
Collaboration across the electrical and mechanical domains leverages more tightly integrated and highly featured tools with richer data formats for greater accuracy and shorter time-to-market.
- Expert Insight Enabling the move to a system-centric view
- Article Tackling the design challenges of PCIe 5.0
Article Implementing high performance, low power Bluetooth Low Energy interfaces in SoCs
A look at the complexiites of implementing a Bluetooth Low Eenergy interface in an SoC.
- Article Introduction to the Compute Express Link (CXL) device types
- Article Introducing the Compute Express Link (CXL) standard: the hardware
Expert Insight Vehicle autonomy and electrification: a perfect match
Is it worth building sophisticated autonomous driving systems if their power consumption reduces an electric vehicle’s range? Maybe yes.
- Article Ensuring system-level security of complex SoCs
- Article Enabling embedded multicore systems with multiple OSes and critical goals
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