Latest
Putting it all together to accelerate 3D IC design
Learn how connectivity management solutions help you manage the multiple formats in which 3D IC components are delivered.-
Connect SystemC models using UVM Connect
Interactive checks mean faster, more accurate symmetry verification
Let there be no misunderstanding: Verifying CXL cache coherency
Guides
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Monolithic 3DIC for SoC
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
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Interconnect resistance
A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.
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Real-number or wreal modeling
Real-valued modelling provides a way of speeding up the simulation of SoCs with significant analog content through the use of discrete-event solvers.
Expert Insights
Give the people what they want: toward making 3D IC mainstream
Learn more about the five interconnected workflows that are democratizing next generation design in the emerging chiplet age.
Reliability verification simplified for multi-power domain designs
Automating reliability verification with tools that offer packaged checks provides greater consistency and accuracy across an increasingly complex process.
A three-phase strategy to master the supply chain tsunami
Knowledge, intelligence and optimization are key to managing the logistical disruption seen since the Covid-19 outbreak.
EDA
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Expert Insight Rising to the verification challenge of open source
Fast emerging options, like RISC-V, could foster massive growth in design but verification still needs commercial tools, a Semicon West panel found.
- Article Building confidence and flexibility in 3D-IC system level design
- Expert Insight NVMe-oF – The future of cloud storage
PCB
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Expert Insight May the Cloud be with you
How to unify your design team to defeat the dark side of board systems design.
- Article The five pillars of digital transformation for electronics system design
- Expert Insight The best in 2020 PCB design
IP
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Article Formal verification for SystemC/C++ designs
Automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis. This tutorial, first presented at DVCon Europe explores how these formal techniques can be deployed and provides real-world examples.
- Article Resolving IP cell-name conflicts peacefully
- Article How to use runtime monitoring for automotive functional safety
Embedded
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Expert Insight Keeping up with rapid innovation in cockpit domain controllers
Automotive cockpit design is being driven forward by prevailing trends in the wider market.
- Expert Insight Use digitalization to mitigate the automotive MCU shortage
- Expert Insight Implementing medical device security for optimal outcomes
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