Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
Doc Formal describes a strategy developed by his company Axiomise to apply formal verification proofs to open-source processor for safety, security and reliability.
In conversation with author and SEMICON West/ES Design West keynoter Bob Pearson on the challenges facing tech on external and internal communication.
Integrated design environments and features within them such as auto-complete deliver valuable efficiencies for input, verification and debut.
Expert Insight Speed up design and verification with a smaller layout
How to remove or extract portions of a layout for easier, more focused and faster project delivery.
- Expert Insight Why hyperlinks are essential for HDL debugging
- Expert Insight How emulation’s virtual mode boosts productivity: Part Two
Expert Insight Enabling the move to a system-centric view
Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.
- Article Tackling the design challenges of PCIe 5.0
- Article How Channel Operating Margin helps Gigabit Ethernet PCB analysis
Article Understanding DDR SDRAM memory choices
This article explains which form of DRAM memory is best for your SoC application, comparing DDR variants, types of DIMM, mobile and low-power versions, graphics memory and 3D stacks.
- Expert Insight High-level synthesis for AI: Part One
- Article Using advanced IP to build SoCs for hyperscale data centres
Article Accelerating the implementation of application-specific processors
Application-specific processors can provide high performance for specialised tasks at low energy cost.
- Article Optimizing the hardware implementation of machine learning algorithms
- Article The antifuse advantage for one-time programmable non-volatile memory
View All Sponsors