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Digital Twin Capital Electrical Compliance

A digital twin methodology to de-risk aerospace electrical design compliance

The digital twin and automation help designers manager increasing aerospace design complexity driven by burgeoning electrification.

Guides

  • Portable stimulus

    EDA - Standards, Technologies

    Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.

  • Dynamic power optimization

    EDA - Techniques

    FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.

  • Monolithic 3DIC for SoC

    EDA - Technologies

    Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.

Expert Insights

Dennis Joseph

Speed up design and verification with a smaller layout

Dennis Joseph is a technical marketing engineer supporting Calibre interfaces in the Design-to-Silicon division of Mentor, a Siemens business. His primary focus is the support and enhancement of the Calibre DESIGNrev layout viewer. Dennis received an M.S. in Electrical and Computer Engineering from the University of Florida.

How to remove or extract portions of a layout for easier, more focused and faster project delivery.

Tom Anderson

Why hyperlinks are essential for HDL debugging

Text editors have major debug limitations that the use of hyperlinks in integrated development environments help you overcome.

Lauro Rizzatti and Gabriele Pulini

How emulation’s virtual mode boosts productivity: Part Two

Part two of this feature describes three use-cases that exploit the VirtuaLAB technology in HDMI, PCIe and Ethernet designs.

EDA

  1. Dr Lauro Rizzatti is a verification consultant and industry expert on hardware emulation. Gabriele Pulini is a product marketing manager in the Emulation Division of Mentor.
    Expert Insight How emulation’s virtual mode boosts productivity: Part One

    This two-part article describes advantages when using a hardware emulation platform in virtual mode compared with in-circuit-emulation.

  2. Expert Insight High-level synthesis for AI: Part Two
  3. Expert Insight High-level synthesis for AI: Part One

PCB

  1. Expert Insight Enabling the move to a system-centric view

    Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.

  2. Article Tackling the design challenges of PCIe 5.0
  3. Article How Channel Operating Margin helps Gigabit Ethernet PCB analysis

IP

  1. Article Understanding DDR SDRAM memory choices

    This article explains which form of DRAM memory is best for your SoC application, comparing DDR variants, types of DIMM, mobile and low-power versions, graphics memory and 3D stacks.

  2. Article Using advanced IP to build SoCs for hyperscale data centres
  3. Article Accelerating the implementation of application-specific processors

Embedded

  1. Article Optimizing the hardware implementation of machine learning algorithms

    Optimizing the way in which machine learning algorithms are implemented in hardware will be a major differentiator for SoCs, especially for edge devices.

  2. Article The antifuse advantage for one-time programmable non-volatile memory
  3. Expert Insight Understanding USB 3.2 and Type-C

Briefing

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
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