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Critical Area Analysis Feature - Featured Image

How critical area analysis improves yield

CAA is a valuable tool available to both design engineers and foundries to help them avoid layout-dependent effects during manufacturing.

Guides

  • Portable stimulus

    EDA - Standards, Technologies

    Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.

  • Dynamic power optimization

    EDA - Techniques

    FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.

  • Monolithic 3DIC for SoC

    EDA - Technologies

    Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.

Expert Insights

High-level synthesis for AI: Part Two

How Chips&Media used HLS on the development of a computer vision IP block.

High-level synthesis for AI: Part One

The computational and algorithmic demands made by computer vision systems highlight HLS' value for AI system development.

Bob Smith

Enabling the move to a system-centric view

Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.

EDA

  1. Ashish Darbari is CEO of formal verification consultancy Axiomise.
    Expert Insight Doc Formal answers 11 key questions

    The doctor was ‘in’ during last month’s DVCon and here highlights some of the main issues in formal raised by delegates at the verification conference.

  2. Article Practical mixed-signal defect and fault injection automation and simulation
  3. Article Fast, accurate layout merging for SoC flows

PCB

  1. PCI_Express_logo
    Article Tackling the design challenges of PCIe 5.0

    Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.

  2. Article How Channel Operating Margin helps Gigabit Ethernet PCB analysis
  3. Expert Insight The Wally Rhines interview – Part Two: AI, automotive and security

IP

  1. Article Understanding DDR SDRAM memory choices

    This article explains which form of DRAM memory is best for your SoC application, comparing DDR variants, types of DIMM, mobile and low-power versions, graphics memory and 3D stacks.

  2. Article Using advanced IP to build SoCs for hyperscale data centres
  3. Article Optimizing the hardware implementation of machine learning algorithms

Embedded

  1. Article The antifuse advantage for one-time programmable non-volatile memory

    Antifuse-based OTP NVM is highly scalable, has the area efficiency to enable macros  of megabit capacities, and offers low read power.

  2. Expert Insight Understanding USB 3.2 and Type-C
  3. Article Using threat models and risk assessments to define device security requirements

Briefing

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