Latest

Optimize your database with duplicate data deletion

Whether you use OASIS or GDSII, unwanted duplicate cells can make their way into the final SoC database. Learn how to remove them.

Guides

  • Portable stimulus

    EDA - Standards, Technologies

    Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.

  • Dynamic power optimization

    EDA - Techniques

    FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.

  • Monolithic 3DIC for SoC

    EDA - Technologies

    Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.

Expert Insights

Tom Anderson

Take advantage of the automated refactoring of design and verification code

Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

Refactoring saves time and resuources by converting code to a common format and eliminates redundancies to make it more readable and maintainable.

Ron Press

Achieving more efficient hierarchical DFT for Arm subsystems

Hierarchical DFT for Arm-based SoCs is easier than ever with the arrival of a complete reference flow from Mentor and Arm.

Ashish Darbari

Spreading the word on formal in Bangalore

Doc Formal rounds up some of the the key observations about verfication made during July’s Synopsys VC Formal SIG event in India.

EDA

  1. Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.
    Expert Insight Correct design and verification coding errors as you type

    An IDE designed to catch typographical errors, missing declarations and inconsistent references in your code can hugely reduce your time in debug.

  2. Expert Insight A new formal proof kit for RISC-V processors
  3. Expert Insight Speed up design and verification with a smaller layout

PCB

  1. Expert Insight Enabling the move to a system-centric view

    Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.

  2. Article Tackling the design challenges of PCIe 5.0
  3. Article How Channel Operating Margin helps Gigabit Ethernet PCB analysis

IP

  1. Portable Stimulus - Three Axes of reuse - Featured Image
    Article Focus your use of Portable Stimulus on three key axes

    Portable Stimulus allows reuse along horizontal, vertical and technique axes, but you need to be aware of the strengths and weaknesses of each to get the greatest benefits.

  2. Article Understanding DDR SDRAM memory choices
  3. Expert Insight High-level synthesis for AI: Part One

Embedded

  1. Article Accelerating the implementation of application-specific processors

    Application-specific processors can provide high performance for specialised tasks at low energy cost.

  2. Article Optimizing the hardware implementation of machine learning algorithms
  3. Article The antifuse advantage for one-time programmable non-volatile memory

Briefing

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