Latest

place and route in design automated hotspot fixing

How to achieve fast, automated, sign-off verification of DFM hotspot fixes in P&R

A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.

Guides

  • Portable stimulus

    EDA - Standards, Technologies

    Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.

  • Dynamic power optimization

    EDA - Techniques

    FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.

  • Monolithic 3DIC for SoC

    EDA - Technologies

    Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.

Expert Insights

Tom Anderson

VHDL users also deserve efficient design and verification

Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

More commonly associated with SystemVerilog, IDEs can also greatly help users of the popular HDL for FPGA, mil/aero and other designs.

Lauro Rizzatti

Covid-19 rings changes for virtual working

Virtualization is becoming ever more common during the Covid-19 outbreak, even for complex technologies like emulation, and showing its strengths.

Adnan Hamid

Security: Making the unknown, known

How to combine formal and dynamic verification within an app to uncover security vulnerabilities.

EDA

  1. CMP simulation dummy fill featured image
    Article Keep chip designs on the level with CMP simulation and dummy fill optimization

    This case study shows how rising CMP simulation quality can be leveraged to detect the position and type of planarity hotspots before manufacture and verify the planarity of a layout.

  2. Expert Insight How to gain a competitive edge with advanced DFT
  3. Article How to achieve accurate reset domain crossing verification

PCB

  1. ECAD-MCAD collaboration - featured image
    Article The necessity and benefits of ECAD-MCAD collaboration for PCB design

    Collaboration across the electrical and mechanical domains leverages more tightly integrated and highly featured tools with richer data formats for greater accuracy and shorter time-to-market.

  2. Expert Insight Enabling the move to a system-centric view
  3. Article Tackling the design challenges of PCIe 5.0

IP

  1. Article Implementing high performance, low power Bluetooth Low Energy interfaces in SoCs

    A look at the complexiites of implementing a Bluetooth Low Eenergy interface in an SoC.

  2. Article Introduction to the Compute Express Link (CXL) device types
  3. Article Introduction to the Compute Express Link (CXL) protocols

Embedded

  1. Scot Morrison Mentor
    Expert Insight Delivering on security for Linux-based medical devices

    How should you address the monitoring and resource challenges in maintaining security for Linux devices.

  2. Expert Insight Choosing an embedded operating system
  3. Expert Insight System-of-systems validation for automotive design

Briefing

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