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Fly the friendly skies with automated CDC verification for DO-254

CDC-related metastability is hard to catch by hand and processes are error prone. Tools offer a more comprehensive approach.

Monolithic 3DIC for SoC

EDA - Technologies
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
Interconnect resistance

EDA - Techniques
A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.
Real-number or wreal modeling

EDA - Techniques
Real-valued modelling provides a way of speeding up the simulation of SoCs with significant analog content through the use of discrete-event solvers.

James Paris

What are the options and how do you balance overarching CAD requirements and personal preferences?

Wu Yang

Both 3D IC and 2.5D IC techniques are being used on more designs and the DFT infrastructure is evolving to meet the challenges they pose.

Tom Anderson

Automating executable specifications as they evolve can deliver major efficiencies.

Expert Insight Use digitalization to mitigate the automotive MCU shortage
The Covid-driven MCU shortage for ECUs and elsewhere in vehicle design can bring entire production lines to a halt if not properly managed.
Expert Insight Aim for power first for best place-and-route results
Expert Insight Siemens’ Sawicki puts priority on scaling in processes, productivity and systems

Expert Insight May the Cloud be with you
How to unify your design team to defeat the dark side of board systems design.
Article The five pillars of digital transformation for electronics system design
Expert Insight The best in 2020 PCB design

Article Formal verification for SystemC/C++ designs
Automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis. This tutorial, first presented at DVCon Europe explores how these formal techniques can be deployed and provides real-world examples.
Article Resolving IP cell-name conflicts peacefully
Article How to use runtime monitoring for automotive functional safety

Expert Insight Implementing medical device security for optimal outcomes
Describing a security strategy that pulls on best practices and standards to ensure medical device approval and the best patient outcomes.
Expert Insight How to choose between a hypervisor and a multicore framework
Expert Insight Taking your first steps in leveraging the RISC-V toolchain

August 3, 2022

Imperas Software has published an open-source functional-coverage library for RISC-V cores.

August 3, 2022

Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.

July 19, 2022

Teledyne e2v has demonstrated a prototype optical link that the company believes could replace electrical signaling for remote RF heads.

July 18, 2022

As the project that funded OpenRoad draws to a close, experts pondered its wider future at the 59th DAC.

July 14, 2022

Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.

July 13, 2022

Siemens has launched Calibre DRC engines that make it easier to perform useful checks early in the layout process.