Latest
Fly the friendly skies with automated CDC verification for DO-254
CDC-related metastability is hard to catch by hand and processes are error prone. Tools offer a more comprehensive approach.-
A quick and easy way to calculate P2P resistance and current density
Why comprehensive memory layout verification needs automated reliability checks
Assure diagnostic coverage from RTL to gate level during analysis for functional safety
Guides
-
Portable stimulus
Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
-
Dynamic power optimization
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
-
Monolithic 3DIC for SoC
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
Expert Insights
Layout customization improves productivity in design and verification flows
What are the options and how do you balance overarching CAD requirements and personal preferences?
Toward usable and scalable DFT for 3D IC design
Both 3D IC and 2.5D IC techniques are being used on more designs and the DFT infrastructure is evolving to meet the challenges they pose.
Executable specifications boost SoC and IP efficiency
Automating executable specifications as they evolve can deliver major efficiencies.
EDA
-
Expert Insight Use digitalization to mitigate the automotive MCU shortage
The Covid-driven MCU shortage for ECUs and elsewhere in vehicle design can bring entire production lines to a halt if not properly managed.
- Expert Insight Aim for power first for best place-and-route results
- Expert Insight Siemens’ Sawicki puts priority on scaling in processes, productivity and systems
PCB
-
Expert Insight May the Cloud be with you
How to unify your design team to defeat the dark side of board systems design.
- Article The five pillars of digital transformation for electronics system design
- Expert Insight The best in 2020 PCB design
IP
-
Article Formal verification for SystemC/C++ designs
Automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis. This tutorial, first presented at DVCon Europe explores how these formal techniques can be deployed and provides real-world examples.
- Article Resolving IP cell-name conflicts peacefully
- Article How to use runtime monitoring for automotive functional safety
Embedded
-
Expert Insight Implementing medical device security for optimal outcomes
Describing a security strategy that pulls on best practices and standards to ensure medical device approval and the best patient outcomes.
- Expert Insight How to choose between a hypervisor and a multicore framework
- Expert Insight Taking your first steps in leveraging the RISC-V toolchain
PLATINUM SPONSORS
View All Sponsors