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Resolving IP cell-name conflicts peacefully

One roadblock to the integration of IP from multiple vendors into an SoC is the likelihood of finding duplicate cell names in the merged design. Carefully considered renaming strategies can fix the problem without causing design database bloat.

Guides

  • Portable stimulus

    EDA - Standards, Technologies

    Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.

  • Dynamic power optimization

    EDA - Techniques

    FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.

  • Monolithic 3DIC for SoC

    EDA - Technologies

    Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.

Expert Insights

Dina Medhat

Not using reliability check waivers? You’re wasting valuable time

Dina Medhat - Mentor

Reliability rule checks need - and now get - more granular analysis that allows designers to adopt proposed waivers with much greater confidence.

Jeff Hancock

How to choose between a hypervisor and a multicore framework

And when this key architectural decision might involve combining both depending on your design’s use-case and demands placed upon it.

Tom Anderson

Extract benefit from the automated refactoring of VHDL code

VHDL has come a long way in terms of complexity. An integrated development environment helps you deliver better and more compliant code quickly.

EDA

  1. Ashish Darbari is CEO of formal verification consultancy and training provider Axiomise.
    Expert Insight Everything you ever wanted to know about RISC-V architectural formal verification

    But you were NOT afraid to ask….

    It’s time for some answers.

  2. Expert Insight Creating a new paradigm for circuit verification
  3. Expert Insight EDA innovation is the foundation of progress

PCB

  1. Matthew Walsh is a Product Marketing Manager in the Electronic Board Systems (EBS) Product Division of Mentor, a Siemens Business
    Expert Insight Don’t get lost in the cloud

    Mentor is rolling out an comprehensive cloud-based design infrastructure feeding into digital twin strategies.

  2. Article The necessity and benefits of ECAD-MCAD collaboration for PCB design
  3. Expert Insight Enabling the move to a system-centric view

IP

  1. runtime monitoring featim
    Article How to use runtime monitoring for automotive functional safety

    The promise of autonomous vehicles is driving profound changes in the design and testing of automotive ICs.

  2. Article Implementing high performance, low power Bluetooth Low Energy interfaces in SoCs
  3. Article Introduction to the Compute Express Link (CXL) device types

Embedded

  1. Pete Decher is the director of Sourcery Tools for the embedded division of Mentor, a Siemens Business. During his 15 years at the company, he was previously a senior product manager and business development manager. Previously, Decher was VP Engineering at Analogy, VP of Engineering at Teseda Corp. and Octavian Scientific, respectively. He holds a MSEE from Stanford University and a BSEE from Georgia Institute of Technology.
    Expert Insight Taking your first steps in leveraging the RISC-V toolchain

    Introducing some of the key links that support the open-source RISC-V ISA with a view toward their use on commercial projects.

  2. Expert Insight Delivering on security for Linux-based medical devices
  3. Expert Insight Choosing an embedded operating system

Briefing

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