Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
Creating strong links between the electrical and mechanical design domains is a leading enabler of digitalization.
Learn how to bring together your NLDM and CCS models to reach timing closure faster with Solido Analytics.
Using on-demand rule checks during place-and-route boosts efficiency and design quality.
DVCon Europe best paper assesses clock design
The best paper at DVCon Europe 2020 analyzed different multiclock strategies for SoCs for their power and flexibility
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Article Resolving IP cell-name conflicts peacefully
One roadblock to the integration of IP from multiple vendors into an SoC is the likelihood of finding duplicate cell names in the merged design. Carefully considered renaming strategies can fix the problem without causing design database bloat.
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Describing a security strategy that pulls on best practices and standards to ensure medical device approval and the best patient outcomes.
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