Putting it all together to accelerate 3D IC designLearn how connectivity management solutions help you manage the multiple formats in which 3D IC components are delivered.
Connect SystemC models using UVM Connect
Interactive checks mean faster, more accurate symmetry verification
Let there be no misunderstanding: Verifying CXL cache coherency
Monolithic 3DIC for SoC
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.
Real-number or wreal modeling
Real-valued modelling provides a way of speeding up the simulation of SoCs with significant analog content through the use of discrete-event solvers.
Shift left to tackle key O-RAN verification challenges
O-RAN compatible Radio Unit (O-RU) and Distributed Unit (O-DU) verification no longer needs to wait until the post-silicon stage.
How to migrate SoC design to the cloud
Moving part of all of a design flow to the cloud involves careful preparation and evaluation as there is no 'one-size-fits-all'.
Give the people what they want: toward making 3D IC mainstream
Learn more about the five interconnected workflows that are democratizing next generation design in the emerging chiplet age.
Expert Insight Reliability verification simplified for multi-power domain designs
Automating reliability verification with tools that offer packaged checks provides greater consistency and accuracy across an increasingly complex process.
- Expert Insight Rising to the verification challenge of open source
- Article Building confidence and flexibility in 3D-IC system level design
Expert Insight A three-phase strategy to master the supply chain tsunami
Knowledge, intelligence and optimization are key to managing the logistical disruption seen since the Covid-19 outbreak.
- Expert Insight May the Cloud be with you
- Article The five pillars of digital transformation for electronics system design
Article Formal verification for SystemC/C++ designs
Automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis. This tutorial, first presented at DVCon Europe explores how these formal techniques can be deployed and provides real-world examples.
- Article Resolving IP cell-name conflicts peacefully
- Article How to use runtime monitoring for automotive functional safety
Expert Insight Keeping up with rapid innovation in cockpit domain controllers
Automotive cockpit design is being driven forward by prevailing trends in the wider market.
- Expert Insight Use digitalization to mitigate the automotive MCU shortage
- Expert Insight Implementing medical device security for optimal outcomes
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