Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.
Real-valued modelling provides a way of speeding up the simulation of SoCs with significant analog content through the use of discrete-event solvers.
What are the options and how do you balance overarching CAD requirements and personal preferences?
Both 3D IC and 2.5D IC techniques are being used on more designs and the DFT infrastructure is evolving to meet the challenges they pose.
Automating executable specifications as they evolve can deliver major efficiencies.
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