Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
How Chips&Media used HLS on the development of a computer vision IP block.
The computational and algorithmic demands made by computer vision systems highlight HLS' value for AI system development.
Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.
Expert Insight Doc Formal answers 11 key questions
The doctor was ‘in’ during last month’s DVCon and here highlights some of the main issues in formal raised by delegates at the verification conference.
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Article Tackling the design challenges of PCIe 5.0
Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.
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Article Understanding DDR SDRAM memory choices
This article explains which form of DRAM memory is best for your SoC application, comparing DDR variants, types of DIMM, mobile and low-power versions, graphics memory and 3D stacks.
- Article Using advanced IP to build SoCs for hyperscale data centres
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The antifuse advantage for one-time programmable non-volatile memory
Antifuse-based OTP NVM is highly scalable, has the area efficiency to enable macros of megabit capacities, and offers low read power.
- Expert Insight Understanding USB 3.2 and Type-C
- Article Using threat models and risk assessments to define device security requirements
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