1. Featured image - Layout merging feature
    Article Fast, accurate layout merging for SoC flows

    How to achieve efficient merging of data from formats such as OASIS, GDS, and OpenAccess to ensure timely verification through DRC runs.

  2. Article Low-power debugging made easy
  3. Expert Insight Emulation for AI: Part One


  1. PCI_Express_logo
    Article Tackling the design challenges of PCIe 5.0

    Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.

  2. Article How Channel Operating Margin helps Gigabit Ethernet PCB analysis
  3. Expert Insight The Wally Rhines interview – Part Two: AI, automotive and security


  1. Article Optimizing the hardware implementation of machine learning algorithms

    Optimizing the way in which machine learning algorithms are implemented in hardware will be a major differentiator for SoCs, especially for edge devices.

  2. Article The antifuse advantage for one-time programmable non-volatile memory
  3. Expert Insight Understanding USB 3.2 and Type-C


  1. Article Using threat models and risk assessments to define device security requirements

    The proliferation of attacks against embedded systems is making designers realize that they need to do more to secure their products and ecosystems.

  2. Expert Insight An open-source framework for greater flexibility in machine-learning development
  3. Expert Insight Flexible embedded vision processing architectures for machine-learning applications



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