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Digital Twin Capital Electrical Compliance

A digital twin methodology to de-risk aerospace electrical design compliance

The digital twin and automation help designers manager increasing aerospace design complexity driven by burgeoning electrification.

Guides

  • Portable stimulus

    EDA - Standards, Technologies

    Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.

  • Dynamic power optimization

    EDA - Techniques

    FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.

  • Monolithic 3DIC for SoC

    EDA - Technologies

    Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.

Expert Insights

The vocal persuader

Former Dell VP Bob Pearson is a strategic consultant with digital marketing agency W2O Group and co-author of multiple books including Crafting Persuasion (with Kip Knight and Ed Tazzia).

In conversation with author and SEMICON West/ES Design West keynoter Bob Pearson on the challenges facing tech on external and internal communication.

Tom Anderson

A helping hand for design and verification

Integrated design environments and features within them such as auto-complete deliver valuable efficiencies for input, verification and debut.

Dennis Joseph

Speed up design and verification with a smaller layout

How to remove or extract portions of a layout for easier, more focused and faster project delivery.

EDA

  1. Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.
    Expert Insight Why hyperlinks are essential for HDL debugging

    Text editors have major debug limitations that the use of hyperlinks in integrated development environments help you overcome.

  2. Expert Insight How emulation’s virtual mode boosts productivity: Part Two
  3. Expert Insight How emulation’s virtual mode boosts productivity: Part One

PCB

  1. Expert Insight Enabling the move to a system-centric view

    Bob Smith of the ESD Alliance describes how we can promote the ongoing evolution of the design ecosystem.

  2. Article Tackling the design challenges of PCIe 5.0
  3. Article How Channel Operating Margin helps Gigabit Ethernet PCB analysis

IP

  1. Article Understanding DDR SDRAM memory choices

    This article explains which form of DRAM memory is best for your SoC application, comparing DDR variants, types of DIMM, mobile and low-power versions, graphics memory and 3D stacks.

  2. Expert Insight High-level synthesis for AI: Part One
  3. Article Using advanced IP to build SoCs for hyperscale data centres

Embedded

  1. Article Accelerating the implementation of application-specific processors

    Application-specific processors can provide high performance for specialised tasks at low energy cost.

  2. Article Optimizing the hardware implementation of machine learning algorithms
  3. Article The antifuse advantage for one-time programmable non-volatile memory

Briefing

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