Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
And when this key architectural decision might involve combining both depending on your design’s use-case and demands placed upon it.
VHDL has come a long way in terms of complexity. An integrated development environment helps you deliver better and more compliant code quickly.
But you were NOT afraid to ask.... It's time for some answers.
Expert Insight Don’t get lost in the cloud
Mentor is rolling out an comprehensive cloud-based design infrastructure feeding into digital twin strategies.
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- Expert Insight Enabling the move to a system-centric view
Article How to use runtime monitoring for automotive functional safety
The promise of autonomous vehicles is driving profound changes in the design and testing of automotive ICs.
- Article Implementing high performance, low power Bluetooth Low Energy interfaces in SoCs
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Expert Insight Taking your first steps in leveraging the RISC-V toolchain
Introducing some of the key links that support the open-source RISC-V ISA with a view toward their use on commercial projects.
- Expert Insight Delivering on security for Linux-based medical devices
- Expert Insight Choosing an embedded operating system
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