NAND flash is a key technology for all systems. 3D techniques now control its cost and potential for future capacity increases.
A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.
Real-valued modelling provides a way of speeding up the simulation of SoCs with significant analog content through the use of discrete-event solvers.
Standard physical verification (PV) check reviews within EDA tools can reduce time-to-tapeout and mitigate risk.
We have the technology. Learn how to 'shift left' with Calibre DesignEnhancer and meet IR, EM and PPA objectives.
Standards-based digital threads will revolutionize design through part models that deliver trust, traceability and context across components.
Article Refreshing the IEEE 1687 IJTAG family for today’s designs
Learn more about how the IJTAG family and associated standards are being enhanced for current challenges.
- Expert Insight Shift left to tackle key O-RAN verification challenges
- Expert Insight How to migrate SoC design to the cloud
Article Putting it all together to accelerate 3D IC design
Learn how connectivity management solutions help you manage the multiple formats in which 3D IC components are delivered.
- Expert Insight A three-phase strategy to master the supply chain tsunami
- Expert Insight May the Cloud be with you
Expert Insight Give the people what they want: toward making 3D IC mainstream
Learn more about the five interconnected workflows that are democratizing next generation design in the emerging chiplet age.
- Article Formal verification for SystemC/C++ designs
- Article Resolving IP cell-name conflicts peacefully
Expert Insight Keeping up with rapid innovation in cockpit domain controllers
Automotive cockpit design is being driven forward by prevailing trends in the wider market.
- Expert Insight Use digitalization to mitigate the automotive MCU shortage
- Expert Insight Implementing medical device security for optimal outcomes
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