Latest
Refreshing the IEEE 1687 IJTAG family for today’s designs
Learn more about how the IJTAG family and associated standards are being enhanced for current challenges.-
Six reasons why you need better cross-platform validation of OASIS layout database generation
Three steps to complete CDC verification
Connect SystemC models using UVM Connect
Guides
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NAND flash
NAND flash is a key technology for all systems. 3D techniques now control its cost and potential for future capacity increases.
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Interconnect resistance
A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.
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Real-number or wreal modeling
Real-valued modelling provides a way of speeding up the simulation of SoCs with significant analog content through the use of discrete-event solvers.
Expert Insights
Improved power management and faster time to market?
We have the technology. Learn how to 'shift left' with Calibre DesignEnhancer and meet IR, EM and PPA objectives.
Welcome to the part model era
Standards-based digital threads will revolutionize design through part models that deliver trust, traceability and context across components.
Shift left to tackle key O-RAN verification challenges
O-RAN compatible Radio Unit (O-RU) and Distributed Unit (O-DU) verification no longer needs to wait until the post-silicon stage.
EDA
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Expert Insight How to migrate SoC design to the cloud
Moving part of all of a design flow to the cloud involves careful preparation and evaluation as there is no ‘one-size-fits-all’.
- Expert Insight Give the people what they want: toward making 3D IC mainstream
- Article Putting it all together to accelerate 3D IC design
PCB
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Expert Insight A three-phase strategy to master the supply chain tsunami
Knowledge, intelligence and optimization are key to managing the logistical disruption seen since the Covid-19 outbreak.
- Expert Insight May the Cloud be with you
- Article The five pillars of digital transformation for electronics system design
IP
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Article Formal verification for SystemC/C++ designs
Automated formal technologies can be used to ease the debug and functional verification burden of SystemC/C++ code prior to high-level synthesis. This tutorial, first presented at DVCon Europe explores how these formal techniques can be deployed and provides real-world examples.
- Article Resolving IP cell-name conflicts peacefully
- Article How to use runtime monitoring for automotive functional safety
Embedded
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Expert Insight Keeping up with rapid innovation in cockpit domain controllers
Automotive cockpit design is being driven forward by prevailing trends in the wider market.
- Expert Insight Use digitalization to mitigate the automotive MCU shortage
- Expert Insight Implementing medical device security for optimal outcomes
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