Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
Text editors have major debug limitations that the use of hyperlinks in integrated development environments help you overcome.
Part two of this feature describes three use-cases that exploit the VirtuaLAB technology in HDMI, PCIe and Ethernet designs.
This two-part article describes advantages when using a hardware emulation platform in virtual mode compared with in-circuit-emulation.
Article Tackling the design challenges of PCIe 5.0
Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.
- Article How Channel Operating Margin helps Gigabit Ethernet PCB analysis
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Article Understanding DDR SDRAM memory choices
This article explains which form of DRAM memory is best for your SoC application, comparing DDR variants, types of DIMM, mobile and low-power versions, graphics memory and 3D stacks.
- Article Using advanced IP to build SoCs for hyperscale data centres
- Article Accelerating the implementation of application-specific processors
Article Optimizing the hardware implementation of machine learning algorithms
Optimizing the way in which machine learning algorithms are implemented in hardware will be a major differentiator for SoCs, especially for edge devices.
- Article The antifuse advantage for one-time programmable non-volatile memory
- Expert Insight Understanding USB 3.2 and Type-C
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