Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
Innovation is extending the technique's power across areas such as context-aware layout, accounting for multi-patterning and implementing fill.
Delivering physical implementations at new process nodes is getting ever harder. Learn how to stay on track by checking work is rule-compliant as you go.
Creating strong links between the electrical and mechanical design domains is a leading enabler of digitalization.
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How to unify your design team to defeat the dark side of board systems design.
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Article Resolving IP cell-name conflicts peacefully
One roadblock to the integration of IP from multiple vendors into an SoC is the likelihood of finding duplicate cell names in the merged design. Carefully considered renaming strategies can fix the problem without causing design database bloat.
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Describing a security strategy that pulls on best practices and standards to ensure medical device approval and the best patient outcomes.
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