nanowires


May 20, 2021

Denser DRAM looks to flash for inspiration

Unisantis aims to use its vertical transistor design in a novel form of DRAM that could improve density four-fold.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations:
November 9, 2020

IEDM 2020 highlights transistor and interconnect advances

This year's IEDM will feature papers that exploit stacked nanoribbons to reduce CMOS footprint, graphene interconnects that support easier integration, and the variability prospects of 2D semiconductors.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: , ,
October 18, 2017

Sub-10nm finFETs to feature at IEDM

Intel and GlobalFoundries will talk about their post-14nm finFET-based processes at December's IEDM.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: , , ,
May 25, 2015

Shape a major choice for sub-10nm nanowire FETs

TCAD specialist GSS says nanowire transistors look practical down to 5nm but that designers need to carefully explore how the wires are shaped as quantum-confinement effects take hold
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:

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