nanowires

Unisantis aims to use its vertical transistor design in a novel form of DRAM that could improve density four-fold.

This year's IEDM will feature papers that exploit stacked nanoribbons to reduce CMOS footprint, graphene interconnects that support easier integration, and the variability prospects of 2D semiconductors.

Intel and GlobalFoundries will talk about their post-14nm finFET-based processes at December's IEDM.

TCAD specialist GSS says nanowire transistors look practical down to 5nm but that designers need to carefully explore how the wires are shaped as quantum-confinement effects take hold