Work presented at IEDM 2020 shows taking advantage of the IC backside for power and ground for the additional area can deliver further benefits for IR drop and security.
Traditional approaches to via insertion to meet reliability and yield at advanced nodes are giving way to necessary automation.
Early access to tools for new processes is helping Moortec deliver IP to determine the real-time health of on-chip circuits.
Ansys has decided to marry cloud computing with some of the tools used in SoC design that can make use of large amounts of temporary computer power.
Cadence Design Systems has introduced a variant of Voltus that runs transistor-level simulations to check for electromigration and IR-drop problems.
Cadence Design Systems uses parallelism in its Voltus tool to provide faster IR drop analysis and bridge static timing and IC-level power-integrity analysis.
Cadence Design Systems has developed a version of its Spectre FastSpice tool that splits simulation across many computers without manually cutting the design into segments.
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