IR drop


October 24, 2023

Flow evolution for the 3DIC/chiplet age

Chiplet-based 3DIC designs present new challenges for flows that integrate tasks from design exploration to physical verification.
September 28, 2021

Scaling power integrity analysis to match analog content in today’s designs

Siemens introduces mPower to bridge the analog-to-digital gap in IR-drop and EM analysis, reflecting the scaling trends in today's ICs.
December 18, 2020

Backside metal defends against IR drop and side-channel attacks

Work presented at IEDM 2020 shows taking advantage of the IC backside for power and ground for the additional area can deliver further benefits for IR drop and security.
March 27, 2020

Tackling IR drop and EM with a push-button via utlility

Traditional approaches to via insertion to meet reliability and yield at advanced nodes are giving way to necessary automation.
Article  |  Topics: Digital/analog implementation, Blog - EDA  |  Tags: , , , , , ,   |  Organizations:
February 1, 2019

Fast process access gets Moortec onto 7nm

Early access to tools for new processes is helping Moortec deliver IP to determine the real-time health of on-chip circuits.
May 23, 2016

Cloud analysis comes to power grid design

Ansys has decided to marry cloud computing with some of the tools used in SoC design that can make use of large amounts of temporary computer power.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
August 5, 2014

Cadence takes Voltus to transistor level

Cadence Design Systems has introduced a variant of Voltus that runs transistor-level simulations to check for electromigration and IR-drop problems.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
November 12, 2013

Cadence ties IR drop into static timing analysis

Cadence Design Systems uses parallelism in its Voltus tool to provide faster IR drop analysis and bridge static timing and IC-level power-integrity analysis.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
October 9, 2013

Cadence parallelizes FastSpice for large-scale mixed-signal checks

Cadence Design Systems has developed a version of its Spectre FastSpice tool that splits simulation across many computers without manually cutting the design into segments.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:

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