scaling limits

December 16, 2013

Qualcomm’s take on preserving Moore’s Law economics

Industry-wide innovation is required to make scaling cost-effective at 7nm, says Qualcomm's VP of Technology. Time for a fat, cholesterol and MSG-free diet.

Article | Topics: Commentary, Conferences, Design to Silicon, Blog - EDA | Tags: 10nm, 16nm, 20nm, 7nm, BEOL, device scaling, ET-SOI, FD-SOI, finFET, III-V, low-power design, model, scaling limits, silicon germanium | Organizations: IEDM, Qualcomm

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