formal verification

OneSpin is bringing recent product launches to DAC and will have technical experts presenting within the conference's Designer Track.

The formal specialist is extending its line for Intel FPGAs that target areas such as AI/ML and HPC, and building out a RISC-V suite focused on ISA compliance.

Cadence and OneSpin are applying various forms of machine learning to their tools to automate formal verification.

Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.

OneSpin will focus at DVCon on its formal integrity verification platform for the RISC-V open-source which aims to speed up the core's adoption. The company will also feature the solution with a partner at EmbeddedWorld.

DVCon USA is coming soon. Mentor's 2019 involvement includes a keynote from parent Siemens and a tutorial on managing your formal verification processes.

The latest Mentor-commissioned Wilson Research Group study on ASIC and FPGA verification highlights technique adoption and maturity.

In a panel session at June's DAC, Synopsys customers talked about some of the ways they make verification more efficient and bring technologies such as formal, emulation, and simulation together.

Machine learning is gradually moving into implementation and verification tools for EDA.

Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.