formal verification

July 26, 2021

Learn how to apply formal verification to safety-critical aviation designs

A detailed technical overview of formal verification within the context of the DO-254 (ED-80) standard is now available to download.
Article  |  Topics: Verification  |  Tags: , , , , , , ,   |  Organizations:
April 16, 2021

Siemens buys formal start-up OneSpin

The formal apps start-up has built strong positions in automotive and RISC-V and will strengthen Siemens in competition with Cadence.
March 18, 2021

DVCon to stick with virtual for Europe as US event highlights paper award

The best paper awards at this month's DVCon highlighted techniques to streamline verification. The European version in the meantime is looking for paper submissions.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations: ,
December 4, 2020

Analog surges as cause of IC respins (Wilson Functional Verification 2020 – Part Three)

Study may point to new challenges in more bidirectional AMS implementations on SoC-class designs, though formal and emulation help keep respin count in check.
December 1, 2020

Less than one-in-five FPGA projects avoid bug escapes (Wilson Functional Verification 2020 – Part Two)

Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.
October 15, 2020

DVCon Europe: using all the tools at your disposal

Among the papers that will be presented at the end of October, this year's DVCon Europe will demonstrate the benefits of taking good ideas from wherever you can in the pursuit of more effective verification flows.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations: , , ,
July 30, 2020

Second formal check aids deadlock hunting

Arm works with EDA to find new efficiencies based on extra CTL-based check in Questa runs.
Article  |  Topics: Verification  |  Tags: , , , ,   |  Organizations: , ,
July 27, 2020

Open and propietary verification tools home in on RISC-V core quality

DAC provided a forum for the growing number of verification efforts focused on checking the architectural compliance and overall RTL quality of RISC-V processors.
July 16, 2020

Mentor brews up a warm welcome at virtual DAC

Mentor, a Siemens Business, will offer a broad range of technical and market insights at the event – as well as a free virtual coffee for those who visit its virtual booth at the show.
Article  |  Topics: Conferences  |  Tags: , ,   |  Organizations: ,
March 30, 2020

How to update legacy automotive designs for functional safety

Updates to existing designs are often error-prone, though safety tolerances are necessarily tightening. This four-step strategy can help.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors