Accellera has published for public review version 0.1 of a standard designed to help pass clock-domain crossing information between EDA tools.
Real Intent has developed a tool to check design and the potential for circuits to glitch.
Axiomise founder and formal expert Ashish Darbari will present across multiple events at DAC in San Francisco next week.
Synopsys R&D vice president Manish Pandey described the ways in which the tools supplier has harnessed machine learning so far to gain speedups and improvements in coverage.
The formal specialist is offering courses across six tiers, including case studies and lab work, with immediate availability.
A detailed technical overview of formal verification within the context of the DO-254 (ED-80) standard is now available to download.
The formal apps start-up has built strong positions in automotive and RISC-V and will strengthen Siemens in competition with Cadence.
The best paper awards at this month's DVCon highlighted techniques to streamline verification. The European version in the meantime is looking for paper submissions.
Study may point to new challenges in more bidirectional AMS implementations on SoC-class designs, though formal and emulation help keep respin count in check.
Less than one-in-five FPGA projects avoid bug escapes (Wilson Functional Verification 2020 – Part Two)
Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.
View All Sponsors