Copper’s future is troubled but it’s likely to stick around

By Chris Edwards |  No Comments  |  Posted: January 15, 2021
Topics/Categories: Blog - EDA  |  Tags: , , , , , ,  | Organizations: , , , ,

The metal has done sterling service for 20 years but the time is approaching to find a replacement for copper as problems with parasitics continue to build up, work presented at last month’s IEDM shows. But it’s not an obvious switch.

In a question-and-answer session for his invited talk at IEDM, Ming-Han Lee, who leads the BEOL pathfinding team at TSMC, said: “As long as [the fill process] is doable, copper is still better than the other metals out there. The maturity of the process and the challenges to enable new materials mean that for the near term, pushing copper to its limit is still good. Eventually, in terms of the gap-fill challenge or performance point of view, we will have to find a new conductor.”

A major issue that has plagued copper since its introduction is the need for a barrier layer to prevent the conductor leaching into the surrounding dielectric. As line widths continue to scale down, the proportion taken up by the more barrier grows, which increases the overall resistance. With scaling, capacitance continues to increase. However, there is some possible respite from a combination of design and process changes. “Capacitance is more sensitive to trench width than trench height,” Lee noted.

Assuming deeper etches are feasible in lower metal layers, a potential way forward is to exploit that differential in capacitance and simply make the lines taller. This need not be a one-size-fits-all approach.

Staggered interconnect

One design-led way in which Intel engineers have proposed to deal with the parasitics in existing copper processes is to interleave two different types of trace in a single layer. The approach relies on the observation that not all circuit paths will benefit in the same way from any reductions in capacitance. So, rather than give each parallel line the same height, the staggered approach has alternating tall and short lines: the short lines sit on top a taller stack of dielectric material.

The overall effect, according to Intel is a reduction in net capacitance between lines. In effect the tall lines, which would be reserved for signals more susceptible to crosstalk are spaced further apart, separated by lines that are not as tall. Simulations showed register files and memory arrays can benefit from the structure by assigning decoder and wordline signals to the taller interconnect. Bitlines would use the shorter traces. According to the team, the technique should make it possible to pack more traces into a smaller area without worsening RC delays.

A process-level option direction is to focus on vias, which have a strong effect on signal delay because of the tendency to exploit the low resistance of the middle metal layers for long-distance traces. Professor Azad Naeemi of the Georgia Institute of Technology said one option is to change materials so that the barrier at the bottom of each via can be reduced in thickness if not completely removed.

“Historically, we didn’t see much impact from via resistance. But now it’s much more significant. As we increase aspect ratios [to accommodate taller, thin interconnects], via resistance will become even more important,” Naeemi said.

Thinning the barrier layers in vias can improve circuit frequency by 10 per cent, according to the work by Georgia Tech in collaboration with Samsung. “With an interconnect-dominated, the improvement is even more significant.”

Layer selection

Not all the vias need have the processing changed to accommodate thinner barrier layers. On an AES test circuit, targeting just minimum-pitch interconnect layers saw close to a 6 per cent improvement in performance compared to 9 per cent for doing it on all layers. Other circuits, such as LPDC, however, did not benefit as much. “For LDPC, improving wires is more important than vias,” Naeemi said.

The more radical change is to change to different metals that do not need barrier layers, such as ruthenium, which is already being investigated by a number of teams as a copper replacement for both vias and wires. “With ruthenium at an 18nm pitch, there is a small improvement in line resistance [compared to copper]. But you see major improvements in vias largely because it doesn’t need barrier layers,” Naeemi noted.

Professor Daniel Gall and colleagues at Resselaer University examined the materials properties of metals such as ruthenium and iridium to gauge which might be the better option to substitute for copper. At the dimensions proposed for their introduction, scattering caused by grain boundaries and line variations have a dramatic effect. In this scenario a low mean free path makes rhodium and iridium look good, with cobalt and ruthenium also outperforming copper, at least in principle.

Doping grain boundaries may provide copper with a new lease of life as this reduces the problems caused by carriers reflecting off them. But this is an area where simulation still has to match up with physical reality. In general, Gall said, “measured reflection values are much lower than calculated”. The net result is that this discrepancy makes the alternative metals look better than copper, at least right now.

One thing in favor of ruthenium, despite its comparative rarity and cost compared to copper, is that it does not need the same kind of barrier layer. It also seems to be moderately compatible with existing damascene processes. “But high stress may cause pattern distortion,” Lee said.

Though shrinking copper interconnects continue to present challenges, it may take several generations before a firm replacement emerges. And even then, the likelihood is that chipmakers will employ a hybrid strategy, with a rare metal reserved for minimum-pitch lines while copper continues to serve for middle and upper layers.

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