At the VLSI Symposia, researchers described how AI hardware could help dramatically accelerate analog and digital design and not all of it directly through machine learning.
Cadence has developed a stimulus optimizer based on neural networks to try to improve the runtime of constrained-random verification runs.
A Mentor-Samsung collaboration cuts the need for model-based analysis and speeds analysis runtime by as much as 20X.
Mentor has a host of tools - some public, some not - that leverage AI and ML. EVP Joe Sawicki has been describing the strategy behind their development.
Mentor takes the wraps off new machine learning fueled features in its HLS and physical design families ahead of DAC 2019.
Cadence and OneSpin are applying various forms of machine learning to their tools to automate formal verification.
Machine learning is gradually moving into implementation and verification tools for EDA.
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