Tech Design Forum
Purdue University
Purdue University
May 2, 2021
Alternative scaling approaches form VLSI 2021 technology highlights
The upcoming VLSI Symposia will feature a number of papers that show the ways in which novel approaches are going to be needed to continue scaling.
Article | Topics:
Blog - EDA
| Tags:
BEOL
,
device scaling
,
forksheet
,
GAA
,
nanosheet
,
scaling limits
,
thin-film transistors
,
thinned wafers
,
VLSI 2021
| Organizations:
IBM
,
IMEC
,
Intel
,
Purdue University
December 18, 2020
Backside metal defends against IR drop and side-channel attacks
Work presented at IEDM 2020 shows taking advantage of the IC backside for power and ground for the additional area can deliver further benefits for IR drop and security.
Article | Topics:
Blog - EDA
| Tags:
design for security
,
IEDM 2020
,
IR drop
,
power grid
,
side-channel analysis
| Organizations:
Georgia Tech
,
Intel
,
Kobe University
,
Purdue University
Briefing Topics
EDA
DFT
Electrical Design
Embedded
IP
PCB
Expert Insights
PLATINUM SPONSORS
View All Sponsors
twitter
facebook
RSS
Tech Design Forum
Log In
Register
Sponsors
Briefing
EDA
EDA TOPICS
DFM
DFT
ESL
IC Implementation
Verification
MORE EDA
Expert Insights
Guides
EDA Home Page
IP
IP TOPICS
Assembly & Integration
Design Management
Selection
MORE IP
Expert Insights
Guides
IP Home Page
PCB
PCB TOPICS
Design Integrity
Layout & Routing
System Codesign
MORE PCB
Expert Insights
Guides
PCB Home Page
Embedded
EMBEDDED TOPICS
Architecture & Design
Integration & Debug
Platforms
User Experience
MORE EMBEDDED
Expert Insights
Guides
Embedded Home Page
Search