system-in-package


April 4, 2019

ODSA weighs options for chiplet interconnect

An Open Compute Project group working on multichip integration sees a combination of parallel and serial interfaces being important for interchip communication.
June 27, 2018

EDA needs to work on the back end, says Qualcomm

It’s the back-end that needs work as system-level considerations begin to dominate design, Qualcomm’s vice president of engineering said at DAC.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations:
April 10, 2018

Cadence tunes Virtuoso for 5nm and SIP

Cadence Design Systems has made enhancements to its Virtuoso mixed-signal layout tool at both the system-level and nanometer-design levels for its 18.1 release.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations:
April 24, 2015

Do you need more stress (analysis) in your life?

Mentor Graphics is working on technology to analyse the effects of mechanical stress on integrated circuits, describing progress at the company's U2U conference.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations:
March 10, 2015

Douglas Adams 1: Apple Watch 0 (game in progress)

'Bling' for fashionistas and the B Ark lot. Apple Watch limps as the S1 SIP fails to offer convincing battery life. Silicon shortfall still dogs wearables.
Article  |  Topics: Blog Topics, Commentary, General  |  Tags: , , , ,   |  Organizations:

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors