interconnect resistance


April 22, 2020

Analyzing common resistance to deliver design reliability

Automated resistance checks mitigate the increasing complexity involved when analyzing voltage drop, ESD and noise, particularly for analog-heavy designs.
January 7, 2015

CEA-Leti deals with heat issue on monolithic 3DIC

At IEDM 2014, CEA-Leti presented a technique that prevents damage to base-layer transistors in monolithic 3DIC processes. As work progresses, the institute is preparing to receive 3DIC designs in 2017.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: ,
August 18, 2014

Power and clocking at 20nm force changes in FPGAs

Design for the 20nm generation of processes has revealed power and clocking issues for the two major FPGA manufacturers presentations at Hot Chips revealed.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: ,
June 5, 2014

3D and EDA need to make up for Moore’s Law, says Qualcomm

Qualcomm is looking to monolithic 3D and smart circuit architectures to make up for the loss of traditional 2D process scaling as wafer costs for advanced nodes continue to increase.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:

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