thinned wafers

The upcoming VLSI Symposia will feature a number of papers that show the ways in which novel approaches are going to be needed to continue scaling.

Research institute Leti and Soitec have decided to team up to work on a new generation of engineered substrates, such as specialized SOI wafers.

Mentor Graphics is working on technology to analyse the effects of mechanical stress on integrated circuits, describing progress at the company's U2U conference.

3D-IC integration techniques such as the use of TSVs, die stacking and interposers are unlikely to limit performance, according to research from TSMC and IBM

Advanced SOI devices with hybrid channel materials may challenge the finFET's future dominance, says IBM

In the world of power semiconductors, not many companies try to go fabless. The tradeoffs between design and process offer many more options for system-level design, argued Infineon's Reinhard Ploss at the ISS Europe conference.