thinned wafers


July 11, 2018

Leti and Soitec partner for wafer development

Research institute Leti and Soitec have decided to team up to work on a new generation of engineered substrates, such as specialized SOI wafers.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
April 24, 2015

Do you need more stress (analysis) in your life?

Mentor Graphics is working on technology to analyse the effects of mechanical stress on integrated circuits, describing progress at the company's U2U conference.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations:
December 13, 2012

3D-IC integration prospects improving, say IEDM researchers

3D-IC integration techniques such as the use of TSVs, die stacking and interposers are unlikely to limit performance, according to research from TSMC and IBM
Article  |  Topics: Blog Topics, Conferences, Design to Silicon  |  Tags: , , , , , ,   |  Organizations: ,
October 15, 2012

FinFETs face planar fightback at IEDM

Advanced SOI devices with hybrid channel materials may challenge the finFET's future dominance, says IBM
Article  |  Topics: Commentary, Conferences, Blog - EDA  |  Tags: , , , , , ,   |  Organizations: ,
February 27, 2012

System-level design meets power

In the world of power semiconductors, not many companies try to go fabless. The tradeoffs between design and process offer many more options for system-level design, argued Infineon's Reinhard Ploss at the ISS Europe conference.
Article  |  Topics: Commentary, Conferences, Blog - EDA  |  Tags: , , , , ,

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