SIP


July 13, 2020

Heterogeneous integration calls for new approaches

Heterogeneous integration has the potential to overcome the yield and cost challenges presented by the growing headwinds associated with process scaling. But it may take a dramatic rethink in design approaches.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations: , ,
July 8, 2020

Scaling costs tip balance toward chiplets for AMD server processors

In a panel session at VLSI Symposia, AMD described how the economics have come down strongly in favor of multichip integration for multicore server processors.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations:
March 18, 2019

PCI may provide key to OCP chiplet standard

The ODSA Workgroup formed by Netronome and others is looking to adopt the PIPE standard for interconnecting chiplets as it starts work on a proof-of-concept module.
November 6, 2018

Netronome launches chiplet initiative for network-accelerator SIPs

Data-center networking specialist Netronome has recruited a number of silicon makers and IP suppliers to a standard for chiplet designs that can be used in SIPs for edge computers and servers.
Article  |  Topics: Blog - EDA, IP, PCB  |  Tags: , , ,   |  Organizations: , , , ,
June 18, 2017

TSMC encapsulates CoWoS for supersized SiP

TSMC encapsulated the multiple chips assembled on a 1200mm2 silicon substrate to cut the chance of damage from warping with the company's CoWoS2 SiP technology.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , ,   |  Organizations:
June 5, 2017

Mentor builds links for multichip package integration

Mentor, a Siemens business, has formed an alliance with foundries and OSAT providers and launched a flow that brings IC and package design together.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , , , ,   |  Organizations: ,
May 30, 2017

Cadence pulls Virtuoso and Allegro closer for 3DIC

Cadence Design Systems has brought its chip- and PCB-design environments closer together as the shift towards multichip packages gains pace.
Article  |  Topics: Blog - EDA, IP, PCB  |  Tags: , , ,   |  Organizations:
May 19, 2017

FinFET-project growth ‘stunning’ says EDA exec

Machine learning, smarter cars, and the infrastructure to support a sixfold increase in IoT and edge devices have helped push up the number of teams doing finFET designs to more than 100, according to Tom Beckley of Cadence.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
June 1, 2015

Avago and Broadcom: integration of another kind?

Last week's announcement by Avago that it would buy Broadcom looks to be only partly about bulk. The merger could help drive SIP and 3DIC integration.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , , ,   |  Organizations:
May 20, 2014

Vorsprung durch 3D technik for Audi

The automotive sector could become one of the key markets for 3D integration according to the head of Audi's progressive semiconductor program.
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , , , ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors