SIP

The choices for heterogeneous integration are falling into three main families, demonstrated by A*Star at IEDM 2022.

The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.

Chiplets will need models to guarantee heterogenous SiP implementation. A cross-industry working group describes its progress so far.

At December's Design Automation Conference, AMD senior vice president Sam Naffziger provided more insights into the chipmaker’s use of chiplet-based design and manufacture.

University of Florida researcher proposes third-party checks on chiplets to demonstrate they are free of trojans.

Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.

The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.

Heterogeneous integration has the potential to overcome the yield and cost challenges presented by the growing headwinds associated with process scaling. But it may take a dramatic rethink in design approaches.

In a panel session at VLSI Symposia, AMD described how the economics have come down strongly in favor of multichip integration for multicore server processors.

The ODSA Workgroup formed by Netronome and others is looking to adopt the PIPE standard for interconnecting chiplets as it starts work on a proof-of-concept module.