DAC 2018 preview: Mentor
Mentor will be present throughout the DAC program but with a particular focus on machine learning, artificial intelligence and automotive challenges.
2.5DIC
Mentor builds links for multichip package integration
Mentor, a Siemens business, has formed an alliance with foundries and OSAT providers and launched a flow that brings IC and package design together.
VLSI Symposia issue calls for papers
Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits.
Altera boosts density and pipelining in finFET FPGA shift
Altera is using a combination of Intel's 14nm process technology and multidie packaging to boost the logic-cell count for its FPGAs, together with a superpipelining strategy to help balance area and clock speed.
3D-IC focus for GSA’s Taipei Memory+ event next week
Packed one-day event has speakers from Cadence, TSMC, Samsung, Amkor, Advantest and more providing a senior level view of making 3D-IC a reality. Registration closes soon.
DATE: Dark clouds gather over 3D integration, panelist tells conference
The chip industry faces problems as foundries and the packaging industry compete over 3D technologies. If resolved, it could mean a new dawn in ASIC design.
3DIC – the advantages and the challenges of vertical integration
The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.
EDA and IP vendors roll out support for TSMC’s 20nm, 3DIC processes
IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
Event alert: TSMC Open Innovation Platform
With the foundry giant set to take the wraps off its latest flows and innovations in just seven days, remember that you must pre-register to attend its Silicon Valley event. Also here are some pre-event pointers.
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