January 4, 2023
The choices for heterogeneous integration are falling into three main families, demonstrated by A*Star at IEDM 2022.
September 21, 2022
Nvidia revealed at its Fall GTC work the company has done on a bidirectional energy-saving chiplet interconnect that could hit the equivalent of 50Gbit/s per line.
July 28, 2021
A Siemens white paper describes a way of automatically deriving information from 2.5D/3DIC designs to streamline latchup design-rules verification.
July 15, 2021
The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.
July 13, 2020
Heterogeneous integration has the potential to overcome the yield and cost challenges presented by the growing headwinds associated with process scaling. But it may take a dramatic rethink in design approaches.
July 8, 2020
In a panel session at VLSI Symposia, AMD described how the economics have come down strongly in favor of multichip integration for multicore server processors.
June 20, 2018
Mentor will be present throughout the DAC program but with a particular focus on machine learning, artificial intelligence and automotive challenges.
June 5, 2017
Mentor, a Siemens business, has formed an alliance with foundries and OSAT providers and launched a flow that brings IC and package design together.
January 9, 2017
Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits.
June 8, 2015
Altera is using a combination of Intel's 14nm process technology and multidie packaging to boost the logic-cell count for its FPGAs, together with a superpipelining strategy to help balance area and clock speed.