Siemens has published a white paper that examines whether package designers need to adopt IC tools and design styles in the move from organic packages to 2.5DIC packages.
The choices for heterogeneous integration are falling into three main families, demonstrated by A*Star at IEDM 2022.
Nvidia revealed at its Fall GTC work the company has done on a bidirectional energy-saving chiplet interconnect that could hit the equivalent of 50Gbit/s per line.
A Siemens white paper describes a way of automatically deriving information from 2.5D/3DIC designs to streamline latchup design-rules verification.
The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.
Heterogeneous integration has the potential to overcome the yield and cost challenges presented by the growing headwinds associated with process scaling. But it may take a dramatic rethink in design approaches.
In a panel session at VLSI Symposia, AMD described how the economics have come down strongly in favor of multichip integration for multicore server processors.
Mentor will be present throughout the DAC program but with a particular focus on machine learning, artificial intelligence and automotive challenges.
Mentor, a Siemens business, has formed an alliance with foundries and OSAT providers and launched a flow that brings IC and package design together.
Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits.
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