2.5DIC

July 28, 2021

Automate latchup verification for 3DIC

A Siemens white paper describes a way of automatically deriving information from 2.5D/3DIC designs to streamline latchup design-rules verification.
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July 15, 2021

Chiplets to need digital twins for reliability

The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.
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July 13, 2020

Heterogeneous integration calls for new approaches

Heterogeneous integration has the potential to overcome the yield and cost challenges presented by the growing headwinds associated with process scaling. But it may take a dramatic rethink in design approaches.
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July 8, 2020

Scaling costs tip balance toward chiplets for AMD server processors

In a panel session at VLSI Symposia, AMD described how the economics have come down strongly in favor of multichip integration for multicore server processors.
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June 20, 2018

DAC 2018 preview: Mentor

Mentor will be present throughout the DAC program but with a particular focus on machine learning, artificial intelligence and automotive challenges.
June 5, 2017

Mentor builds links for multichip package integration

Mentor, a Siemens business, has formed an alliance with foundries and OSAT providers and launched a flow that brings IC and package design together.
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January 9, 2017

VLSI Symposia issue calls for papers

Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits.
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June 8, 2015

Altera boosts density and pipelining in finFET FPGA shift

Altera is using a combination of Intel's 14nm process technology and multidie packaging to boost the logic-cell count for its FPGAs, together with a superpipelining strategy to help balance area and clock speed.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , ,   |  Organizations:
October 23, 2013

3D-IC focus for GSA’s Taipei Memory+ event next week

Packed one-day event has speakers from Cadence, TSMC, Samsung, Amkor, Advantest and more providing a senior level view of making 3D-IC a reality. Registration closes soon.
March 19, 2013

DATE: Dark clouds gather over 3D integration, panelist tells conference

The chip industry faces problems as foundries and the packaging industry compete over 3D technologies. If resolved, it could mean a new dawn in ASIC design.
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