3DIC

December 31, 2021

AMD moves gradually into 3D integration

At December's Design Automation Conference, AMD senior vice president Sam Naffziger provided more insights into the chipmaker’s use of chiplet-based design and manufacture.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , , , ,   |  Organizations:
October 18, 2021

Three ways to 3D feature at IEDM

Three highlighted papers at IEDM, taking place in December, show the different approaches to the use of the vertical dimension to cut energy use and improve density.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: , , ,
October 7, 2021

Combined database underpins 3DIC design suite

Cadence has built a unified database to support a group of tools to support the planning and implementation of 3DIC designs.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations:
July 28, 2021

Automate latchup verification for 3DIC

A Siemens white paper describes a way of automatically deriving information from 2.5D/3DIC designs to streamline latchup design-rules verification.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
July 15, 2021

Chiplets to need digital twins for reliability

The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
June 4, 2021

IEDM looks for papers across 2D devices to 3DICs

IEDM has issued a call for papers for what the organizers expect to be an in-person event in December.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,
August 25, 2020

TSMC fills in sub-nodes as EUV gains ground

TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , , ,   |  Organizations: ,
July 21, 2020

3D integration technologies will blend says TSMC chief scientist

DTCO and 3D integration will dominate scaling in the coming decade, TSMC chief scientist Philip Wong claimed in his keynote at DAC on Monday
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: ,
July 13, 2020

Heterogeneous integration calls for new approaches

Heterogeneous integration has the potential to overcome the yield and cost challenges presented by the growing headwinds associated with process scaling. But it may take a dramatic rethink in design approaches.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , , ,   |  Organizations: , , ,
October 9, 2018

Synopsys takes TSMC design into the cloud; IP to 7nm, 5nm and automotive processes

Synopsys is taking IC design on TSMC processes into the cloud with the launch of the Synopsys Cloud Solution, which will run on platforms from Synopsys, Amazon Web Services (AWS) or Microsoft Azure.
Article  |  Topics: Design to Silicon, Blog - EDA, IP, - Verification  |  Tags: , ,   |  Organizations: , ,

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