emulation

December 5, 2023

Zero ASIC open sources system simulation/emulation platform

Start-up launches platform on path to the specification, emulation and simulation of large chiplet-based designs.
January 31, 2023

Siemens harnesses machine learning for more comprehensive verification

As first silicon success declines, new software aims to provide a more holistic view of coverage data from multiple sources.
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November 21, 2022

DVCon Europe looks to network effects

Aside from the keynotes and technical papers, the networking at an event like DVCon Europe provides a way to keep open-source EDA on the road.
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October 28, 2021

Emulation’s scheduling challenge

Emulation capacity and its scalability is a major issue for large SoC designs, said panelists at DVCon Europe.
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April 19, 2021

Hardware verification puts software first

Siemens's expansion of the Veloce hardware-assisted verification platform delivers on one of its current mission statements.
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April 6, 2021

Cadence updates emulation and prototyping lineup

Cadence Design Systems has designed a new custom processor for the Z2 emulator and employed Xiliinx UltraScale+ for the prototyping platform.
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March 26, 2021

Siemens brings emulation and prototyping together in hardware-assisted verification

Siemens Digital Industries Software has launched the latest generation of its Veloce hardware-assisted verification systems with a product line that encompasses silicon virtual platform, hardware emulation, and prototyping support.
March 18, 2021

DVCon to stick with virtual for Europe as US event highlights paper award

The best paper awards at this month's DVCon highlighted techniques to streamline verification. The European version in the meantime is looking for paper submissions.
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December 18, 2020

Virtual emulation delivers verification for the latest storage devices

Computational storage devices are posing a new raft of challenges that is being addressed using a powerful pre-silicon methodology.
December 4, 2020

Analog surges as cause of IC respins (Wilson Functional Verification 2020 – Part Three)

Study may point to new challenges in more bidirectional AMS implementations on SoC-class designs, though formal and emulation help keep respin count in check.

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