Cloud access to emulator helps AI processor start-up prove design, win funding
Small startup gets flexible cloud access to big iron to prove a novel processor architecture quickly.
emulation
Open-RAN puts more focus on emulation in testing programs
Recent developments have made Open-RAN look more attractive as a way of implementing 5G systems. This is helping to drive a shift-left in verification and test.
Deploying pre- and post-silicon verification and test for 5G designs
A flexible and still evolving range of 5G standards requires methodologies that can handle massive test.
Siemens and Arm combine to extend digital twin further into SoC design
Partnership combines Siemens PAVE 360 digital twin with ARM IP, including dedicated automotive offerings, to speed and streamline design toward Level 5.
Master the design and verification of next gen transport: Part Four – emulation
Emulation is already playing a vital role in advanced automotive design within a digital twin environment.
Master the design and verification of next gen transport: Part Two – high-level synthesis
An object classification demonstrator shows how high-level synthesis (HLS) can speed the delivery and exploration of automotive design.
Master the design and verification of next gen transport: Part One – overview
What design solutions can best help deliver increasingly complex autonomous and ADAS systems?
Cadence expands Protium for rack-based prototyping
Cadence has developed a version of its Protium prototyping engine that supports larger designs and which is intended to go into data-center racks.
DVCon China 2019 preview: SmartDV
RISC-V VIP offerings headline the verification specialist’s presence in Shanghai later this month.
DVCon USA 2019 preview: SmartDV
The verification IP specialist is focusing on its new products for RISC-V verification and for emulation platforms next week in San Jose.
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