Aside from the keynotes and technical papers, the networking at an event like DVCon Europe provides a way to keep open-source EDA on the road.
Emulation capacity and its scalability is a major issue for large SoC designs, said panelists at DVCon Europe.
Siemens's expansion of the Veloce hardware-assisted verification platform delivers on one of its current mission statements.
Cadence Design Systems has designed a new custom processor for the Z2 emulator and employed Xiliinx UltraScale+ for the prototyping platform.
Siemens Digital Industries Software has launched the latest generation of its Veloce hardware-assisted verification systems with a product line that encompasses silicon virtual platform, hardware emulation, and prototyping support.
The best paper awards at this month's DVCon highlighted techniques to streamline verification. The European version in the meantime is looking for paper submissions.
Computational storage devices are posing a new raft of challenges that is being addressed using a powerful pre-silicon methodology.
Study may point to new challenges in more bidirectional AMS implementations on SoC-class designs, though formal and emulation help keep respin count in check.
A partnership between Siemens and VSI, a real-world autonomous vehicle research company, aims to refine and promote digital twin strategies.
Small startup gets flexible cloud access to big iron to prove a novel processor architecture quickly.
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