Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
The latest Mentor-commissioned Wilson Research Group study on ASIC and FPGA verification highlights technique adoption and maturity.
Struggling with how to make your debug triage process more efficient? A new checklist could help focus your efforts.
IC Manage is expanding its work on big data in EDA with the creation of a labs program that aims to work with clients on novel ideas for analyzing the gigabytes of output from chip-design tools.
Cliosoft sees a merging of social features and design-data repositories as driving more efficient reuse in chipmakers, bringing them together in its recently launched DesignHub product line.
Formal, AI and UVM form key parts of the OneSpin agenda for this year's Design Automation Conference.
The vendor's experiences in enabling concurrent engineering in Xpedition Enterprise contain lessons for all design disciplines.
Cadence Design Systems and The Mathworks have implemented the first phase of an integration program to link tools such as Virtuoso ADE to Matlab.
Mentor's Greg Aldrich describes how test's market leader is driving down cost in the billion-gate era by rethinking and extending existing technologies
Flow exploration helps designers establish best approach to advanced network processor implementation on Samsung finFET process
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