The third part of this series takes the original CNN demonstrator through a full ISO 26262 type functional safety workflow
Mentor has a host of tools - some public, some not - that leverage AI and ML. EVP Joe Sawicki has been describing the strategy behind their development.
A new whitepaper describes some of the techniques you can use to get the most out of cloud-based DRC with Calibre.
Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
The latest Mentor-commissioned Wilson Research Group study on ASIC and FPGA verification highlights technique adoption and maturity.
Struggling with how to make your debug triage process more efficient? A new checklist could help focus your efforts.
IC Manage is expanding its work on big data in EDA with the creation of a labs program that aims to work with clients on novel ideas for analyzing the gigabytes of output from chip-design tools.
Cliosoft sees a merging of social features and design-data repositories as driving more efficient reuse in chipmakers, bringing them together in its recently launched DesignHub product line.
Formal, AI and UVM form key parts of the OneSpin agenda for this year's Design Automation Conference.
The vendor's experiences in enabling concurrent engineering in Xpedition Enterprise contain lessons for all design disciplines.
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