MoS2


August 25, 2020

TSMC fills in sub-nodes as EUV gains ground

TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , , ,   |  Organizations: ,
May 11, 2015

VLSI Symposia delve into future process choices

Intel 14nm finFET SoC process is among the highlights of the 2015 VLSI Symposia alongside research that looks at the integration of III-V and 2D materials for future processes.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , , ,   |  Organizations: , , ,

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