DTCO


August 16, 2018

IBM and Synopsys to apply DTCO to post-finFET process development

Collaboration on DTCO offers IBM a better way to evaluate combinations of transistor architectures, materials and other process technology innovations using design metrics, before real wafers become available for physical experimentation.
June 22, 2018

Imec stacks transistors for denser 3nm option

Imec proposes using stacked CMOS transistors and buried power rails to improve density for the 3nm process node.
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June 22, 2018

GlobalFoundries plays with metal gear in search for solid gains

At VLSI Symposia 2018, GlobalFoundries researchers proposed looking at the metal-gate ‘gear’ ratio as a way of improving the routability of standard cells.
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June 21, 2018

Samsung couples EUV with DTCO for 7nm shrink

Samsung Electronics expects to increase savings on die area in the shift from its 10nm to 7nm node by applying both EUV for critical layers and several layout-focused process changes.
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May 23, 2018

Pillar transistor points to smaller SRAMs at 5nm

Imec and Unisantis Electronics have developed a process flow based on a vertical transistor with a gate on all sides they claim will lead to denser memories on a 5nm node.
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July 22, 2016

IEDM alters schedule to keep abreast of process updates

The International Electron Device Meeting has pushed back the deadline for its papers to get the latest developments in process and device design into the December conference.
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June 20, 2016

DTCO points to sub-10nm optimizations

DTCO work by GlobalFoundries and Qualcomm reported at VLSI Symposia shows the need to minimize fin counts in future finFET processes.
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