April 13, 2023
Intel Foundry Services has signed a deal with Arm that will see the two companies work on a program of system and design-technology co-optimization.
December 9, 2022
Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.
July 5, 2022
Primarius Technologies is making additions to its portfolio of library-design and verification tools at DAC next week.
August 23, 2021
Aiming for a primarily physical event in the fall, organisers of the 2021 IEDM have published the tutorial and short-core schedule.
September 14, 2020
Mentor, a Siemens business, plans to expand the team working on the Aprisa place-and-route tool following the purchase of Avatar Integrated Systems, announced in July.
July 21, 2020
DTCO and 3D integration will dominate scaling in the coming decade, TSMC chief scientist Philip Wong claimed in his keynote at DAC on Monday
August 16, 2018
Collaboration on DTCO offers IBM a better way to evaluate combinations of transistor architectures, materials and other process technology innovations using design metrics, before real wafers become available for physical experimentation.
June 22, 2018
Imec proposes using stacked CMOS transistors and buried power rails to improve density for the 3nm process node.
June 22, 2018
At VLSI Symposia 2018, GlobalFoundries researchers proposed looking at the metal-gate ‘gear’ ratio as a way of improving the routability of standard cells.
June 21, 2018
Samsung Electronics expects to increase savings on die area in the shift from its 10nm to 7nm node by applying both EUV for critical layers and several layout-focused process changes.