standard cell


June 14, 2021

AI’s design speedups, with and without machine learning

At the VLSI Symposia, researchers described how AI hardware could help dramatically accelerate analog and digital design and not all of it directly through machine learning.
June 3, 2021

Three libraries tune speed and density on TSMC’s 3nm process

TSMC will provide three different standard-cell libraries for its upcoming finFET-based 3nm process to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and circuit frequency.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , ,   |  Organizations:
June 25, 2018

Node-variant FinFET tweaks try to improve cost, performance

Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations: , ,
February 28, 2018

Cadence and Imec tape out 3nm interconnect test chip

Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
October 3, 2014

ARM tools take aim at finFET layout, timing issues

ARM has launched a pair of tools designed to improve the density and performance of finFET designs that use the company's physical libraries.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , , ,   |  Organizations:

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