AI’s design speedups, with and without machine learning
At the VLSI Symposia, researchers described how AI hardware could help dramatically accelerate analog and digital design and not all of it directly through machine learning.
standard cell
Three libraries tune speed and density on TSMC’s 3nm process
TSMC will provide three different standard-cell libraries for its upcoming finFET-based 3nm process to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and circuit frequency.
Node-variant FinFET tweaks try to improve cost, performance
Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.
Cadence and Imec tape out 3nm interconnect test chip
Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
ARM tools take aim at finFET layout, timing issues
ARM has launched a pair of tools designed to improve the density and performance of finFET designs that use the company's physical libraries.
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