June 25, 2018
Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.
February 28, 2018
Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
October 3, 2014
ARM has launched a pair of tools designed to improve the density and performance of finFET designs that use the company's physical libraries.