Nvidia's move into software aimed at mask production and EDA looks to be part of a wider shift to improve yields.
Intel expects to double logic density through metal scaling and smaller cells with upcoming process.
Imec's senior vice president of CMOS outlined future directions for the technology over the coming decade.
AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.
Synopsys is taking IC design on TSMC processes into the cloud with the launch of the Synopsys Cloud Solution, which will run on platforms from Synopsys, Amazon Web Services (AWS) or Microsoft Azure.
Samsung Electronics expects to increase savings on die area in the shift from its 10nm to 7nm node by applying both EUV for critical layers and several layout-focused process changes.
Despite the intense R&D going into storage-class and other novel forms of non-volatile memories, flash is set to continue as the bulk memory of choice, Micron executive claims in VLSI Symposia keynote.
New flow enables high-performance, high-integration designs.
Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
Innovation and advances in EUV and OPC lead Mentor's offerings at SPIE in San Jose later this month.
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