June 20, 2022
Intel expects to double logic density through metal scaling and smaller cells with upcoming process.
December 15, 2020
Imec's senior vice president of CMOS outlined future directions for the technology over the coming decade.
June 15, 2020
AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.
October 9, 2018
Synopsys is taking IC design on TSMC processes into the cloud with the launch of the Synopsys Cloud Solution, which will run on platforms from Synopsys, Amazon Web Services (AWS) or Microsoft Azure.
June 21, 2018
Samsung Electronics expects to increase savings on die area in the shift from its 10nm to 7nm node by applying both EUV for critical layers and several layout-focused process changes.
June 20, 2018
Despite the intense R&D going into storage-class and other novel forms of non-volatile memories, flash is set to continue as the bulk memory of choice, Micron executive claims in VLSI Symposia keynote.
May 2, 2018
New flow enables high-performance, high-integration designs.
February 28, 2018
Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
February 16, 2018
Innovation and advances in EUV and OPC lead Mentor's offerings at SPIE in San Jose later this month.
June 18, 2017
EUV and fin optimization help build Samsung's upcoming 7nm process, the company discloses at the VLSI Technology Symposium.