Heterogeneous integration has the potential to overcome the yield and cost challenges presented by the growing headwinds associated with process scaling. But it may take a dramatic rethink in design approaches.
In a panel session at VLSI Symposia, AMD described how the economics have come down strongly in favor of multichip integration for multicore server processors.
AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.
The verification IP is the first to become commercially available for the bus interface backed by companies such as AMD, Google, IBM, Micron and Xilinx.
AI, its system design implications and its impact on EDA tools themselves will be a key theme for ES Design West next month.
AMD used Calibre with optimisations implemented for cloud support to slash runtimes on high-end server processor designs.
DVCon USA is coming soon. Mentor's 2019 involvement includes a keynote from parent Siemens and a tutorial on managing your formal verification processes.
In a panel session at June's DAC, Synopsys customers talked about some of the ways they make verification more efficient and bring technologies such as formal, emulation, and simulation together.
Early-access customers talked about their experiences with the Synopsys Fusion-based flow in a panel session at the DAC.
GlobalFoundries intends to offer a 12nm FinFET process as a stepping stone from its 14nm process.
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