AMD

March 4, 2022

Verification engineers look to better skills to beat schedules

A panel at DVCon argued too much of a focus on point tools coupled with challenges with interoperability and cross-industry cooperation is hindering the ability of SoC teams to design and verify complex products.
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December 31, 2021

AMD moves gradually into 3D integration

At December's Design Automation Conference, AMD senior vice president Sam Naffziger provided more insights into the chipmakerā€™s use of chiplet-based design and manufacture.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , , , ,   |  Organizations:
October 28, 2021

Emulation’s scheduling challenge

Emulation capacity and its scalability is a major issue for large SoC designs, said panelists at DVCon Europe.
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March 26, 2021

Siemens brings emulation and prototyping together in hardware-assisted verification

Siemens Digital Industries Software has launched the latest generation of its Veloce hardware-assisted verification systems with a product line that encompasses silicon virtual platform, hardware emulation, and prototyping support.
July 13, 2020

Heterogeneous integration calls for new approaches

Heterogeneous integration has the potential to overcome the yield and cost challenges presented by the growing headwinds associated with process scaling. But it may take a dramatic rethink in design approaches.
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July 8, 2020

Scaling costs tip balance toward chiplets for AMD server processors

In a panel session at VLSI Symposia, AMD described how the economics have come down strongly in favor of multichip integration for multicore server processors.
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June 15, 2020

EDA in the cloud boosts DRC iterations for AMD

AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.
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July 2, 2019

SmartDV adds verification IP for OpenCAPI data-center standard

The verification IP is the first to become commercially available for the bus interface backed by companies such as AMD, Google, IBM, Micron and Xilinx.
June 13, 2019

The road to ES Design West: AI

AI, its system design implications and its impact on EDA tools themselves will be a key theme for ES Design West next month.
June 6, 2019

Calibre scales to 4000 nodes for faster sign off in the cloud

AMD used Calibre with optimisations implemented for cloud support to slash runtimes on high-end server processor designs.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: , , ,

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