respin

December 4, 2020

Analog surges as cause of IC respins (Wilson Functional Verification 2020 – Part Three)

Study may point to new challenges in more bidirectional AMS implementations on SoC-class designs, though formal and emulation help keep respin count in check.

Article | Topics: Blog Topics, Commentary, Market Research, Verification | Tags: AMS, analog, design management, emulation, formal apps, formal verification, property checking, respin | Organizations: Siemens, Siemens EDA, Wilson Research Group

November 14, 2018

Case study: Achieving earlier signoff convergence and a ‘shift left’ for P&R at Qualcomm

Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.

Article | Topics: Blog - EDA, - GDSII, Verification | Tags: calibre, convergence, design management, DRC, place and route, respin, shift left, signoff | Organizations: Qualcomm, Siemens EDA

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