EDA

About 1,600 new UVM System Verilog verification IP memory models will cut testbench development time and offer more time to increase coverage.

Verification specialist's DVCon activities are headlined by a panel on emulation and static verification.

Mentor Graphics chairman and CEO Wally Rhines will deliver the DVCon keynote as the vendor sets a deep agenda for the conference.

The Calibre vendor will have a strong technical presence at the leading lithography conference taking place in late February in San Jose.

Cadence has use physically aware placement in a test tool that promises less routing congestion for scan test and which increases the potential for stimulus compression.

Driving down energy consumption for the IoT, making portable stimulus deliver real benefits and the practical benefts of a globalizing DVCon.

Researchers describe at IEDM 2015 how they are making gallium nitride fit into a wider range of power-handling applications and may even result in mass-market vertical transistors.

According to ARM's Greg Yeric in his keynote at IEDM, even with cost improvements for multiple patterning, fewer designs will see the benefit of further silicon node scaling. Savings will come from design.

Cadence Design Systems has worked with Lumerical Solutions and PhoeniX Software to develop a flow for designing photonic ICs based on the Virtuoso custom-design platform.

Mentor's Greg Aldrich describes how test's market leader is driving down cost in the billion-gate era by rethinking and extending existing technologies