Cadence joins the dots for verification
The EDA giant has accelerated and integrated its tool suites and broadened its verification IP catalog in its new look System Development Suite.
The EDA giant has accelerated and integrated its tool suites and broadened its verification IP catalog in its new look System Development Suite.
Designers working on mixed-signal circuits will benefit from using digital tools, Cadence’s SVP of R&D for custom design said at CDNLive EMEA today. But for those who don’t a faster fast Spice is on its way.
A startup has analyzed the shape of Intel’s fins and found the process is not quite as well-behaved as circuit designers would perhaps like.
This newsletter highlights recently-added content on the site that addresses the connected areas of verification, prototyping and emulation. We’ve also added more overview EDA Guides on major design flow challenges.
Mentor Graphics’ user event includes insights on constraints-driven design and the emerging OVM verification methodology in an eye-catching program.
Cutting the cabling to simplify the emulation process.
Mentor Graphics has updated its Veloce emulator, using a newly developed chip to double capacity while, at the same time, developing new software to overcome the traditional handicaps of in-circuit emulation.
Xilinx has created Vivado, a new set of tools to support sub-30nm FPGAs that, for advanced designs at least, will take over from its long-established ISE suite.
SpringSoft is trying a different approach to constraint-based design in a bid to improve the automation of custom and mixed-signal design, particularly on advanced process nodes.
Mentor Graphics’ CEO Wally Rhines picked out the trends he says can boost design productivity and drive growth for tools vendors at the company’s Silicon Valley User2User conference