Tech Design Forum Briefing


Briefing Authors

Paul Dempsey

Paul Dempsey Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.

Luke Collins

Luke Collins Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.

Chris Edwards

Chris Edwards Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
June 19, 2018

Exploring the automotive industry’s requirements for data converter IP

What does it take to build data converter IP that will meet the reliability and functional safety requirements of the automotive industry?

June 19, 2018

DAC 2018 preview: ESD Alliance

The Electronic System Design Alliance will discuss its recent decision to join SEMI and highlight DAC’s new Infrastructure Alley.

June 19, 2018

Mentor targets DRC efficiencies for place-and-route with Calibre RealTime Digital

Early users of the new P&R integrated physical verification tool say time-to-sign-off was cut by 40% and above.

June 19, 2018

DAC 2018 preview: Baum

Power analysis specialist will showcase the 2.0 edition of its PowerBaum analysis and modeling suite at DAC.

June 18, 2018

DAC 2018 preview: Synopsys

DAC 2018 will see Synopsys focusing on close links with foundry partners, as well as exploring ways to exploit the potential of machine learning, in both SoC architectures and SoC design flows.

June 18, 2018

DAC 2018 preview: Verific

The parser specialist will demonstrate its recently announced INVIO integration to speed development around VHDL and SystemVerilog.

June 18, 2018

Switch to orbit mode boosts MRAM on 300mm wafers

Imec will at this week’s VLSI Symposia describe how it fabricated a form of magnetic memory suitable for use as a non-volatile cache onto 300mm wafers using CMOS-compatible processes.

June 14, 2018

Accellera signs off on SystemC control standard

Accellera has published version 1.0 of the SystemC Configuration, Control and Inspection (CCI) standard.

June 6, 2018

Synopsys speeds PrimeTime with AI

Synopsys applies AI to speed PrimeTIme, as part of wider strategy to exploit machine learning to ease chip design

May 24, 2018

Case study demonstrates 59% extra power savings for HPC

Taiwanese ASIC specialist Alchip discusses use of Mentor PowerPro for low power on 16nm 24×24 array HPC chip in detail

Previous Blog Posts

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors