Semiwise, a startup founded by University of Glasgow professor Asen Asenov and former CEO of Gold Standard Simulations (GSS), has developed a low-power CMOS transistor technology suitable for ultralow-power sensor nodes.
The formal verification specialist will leverage its recent, successful certification by TÜV SÜD for functional safety solutions.
Innovation and advances in EUV and OPC lead Mentor’s offerings at SPIE in San Jose later this month.
Slovenian startup Red Pitaya has added a front-end module and firmware to its FPGA-based StemLab board to create a customizable vector network analyzer (VNA) and RF tester.
The formal verification specialist will be discussing its own experiences and has partnered with users for presentations at DVCon US.
Breker’s work towards the portable stimulus roll-out will lead much of its offering later this month in San Jose.
By the middle of this year Arm intends to deliver a processor designed specifically for deep-learning pipelines in edge devices, to capitalize on a move away from cloud computing for image and voice recognition.
Simulation suite automates the largely manual process of validating more than 25 SerDes protocols.
The Siemens subsidiary is involved with a wide range of tutorials, technical papers and more at this month’s San Jose conference.
Traditional functional coverage has run out of steam and novel methods to improve the understanding of what tests are doing are needed to make progress. That is the view of Greg Smith, director of verification innovation and methodology improvement at Oracle.
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