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TestKompress
December 4, 2015
Three key ways to reduce silicon test costs
Mentor's Greg Aldrich describes how test's market leader is driving down cost in the billion-gate era by rethinking and extending existing technologies
Article | Topics:
Blog - EDA
,
- General
,
Tested Component to System
| Tags:
ATPG
,
automotive
,
design cost
,
design management
,
ISO26262
,
pattern count
,
Tessent
,
test
,
test compression
,
test points
,
TestKompress
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Intel
,
Mentor Graphics
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