Tech Design Forum
Briefing
hyperbus
hyperbus
March 1, 2016
Mentor builds out verification IP for memory
About 1,600 new UVM System Verilog verification IP memory models will cut testbench development time and offer more time to increase coverage.
Article | Topics:
Blog - EDA
,
IP
,
- Tested Component to System
,
Verification
| Tags:
DRAM
,
enterprise verification platform
,
flash
,
hyperbus
,
Questa
,
SystemVerilog
,
test bench
,
test case
,
UCIS
,
UVM
,
verification IP
| Organizations:
Cypress Semiconductor
,
Mentor Graphics
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