EDA Topics

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  Eight requirements for 3D-IC design

  Many design teams are looking at ways in which they can make use of 3D integration. Here are eight requirements for an effective 3D-IC design flow.

  Topics/Categories: EDA - DFM, IC Implementation
  

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  Physical verification of finFET and FD-SOI devices

  A look at some of the design and physical verification challenges of working with finFET and FD-SOI devices, including their impact on layout, DRC and LVS.

  Topics/Categories: EDA - Verification
  

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  The five key challenges of 20nm custom and analog design

  The arrival of the 20nm and finFET-based sub-20nm processes bring with them challenges for custom IC design. These are the five key areas and a methodology that can address them.

  Topics/Categories: EDA - DFM, IC Implementation
  

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  3D-IC integration – a stepwise approach

  2.5D-IC integration overcomes 2D limitations such as cost, offchip bandwidth bottlenecks and I/O pin scarcity, and offers a route to true 3D-IC integration.

  Topics/Categories: EDA - IC Implementation
  

DFM

1. Article Eight requirements for 3D-IC design
2. Article The five key challenges of 20nm custom and analog design
3. Expert Blog Time to take up the 3D integration challenge

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DFT

1. Expert Blog Building an RTL sign-off flow
2. Expert Blog IJTAG: delivering an industry platform for IP test and integration
3. Article 20nm test demands new design-for-test and diagnostic strategies

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ESL

1. Expert Blog Focus on product creation for effective design
2. Article Get more out of system architectures
3. Article The Shift Left: how virtual prototyping reduces risk

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IC Implementation

1. Article Eight requirements for 3D-IC design
2. Article The five key challenges of 20nm custom and analog design
3. Article 3D-IC integration – a stepwise approach

More

Verification

1. Expert Blog Building an RTL sign-off flow
2. Expert Blog Better analysis helps improve design quality
3. Article Physical verification of finFET and FD-SOI devices

More