EDA vendors and internal CAD teams use Verific parsers for tool development. Here’s how one company developed its strategy for this popular technology.
We look at how best to leverage both software debug tools and emulators, the limitations to traditional techniques, and the drive toward offline debug.
The ISO 26262 safety standard lays out a number of best practices for the automotive industry and for suppliers. Formal verification provides a way of streamlining the verification of SoCs that need to conform to the standard.
A change in the way the core compact models are developed has accelerated their development and, for the first time, allowed the models to be used not just for circuit simulation but to help guide process evolution as chipmakers play not only with materials but the shape of finFETs.
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