Bus contention and floating busses are well defined issues and therefore excellent candidates for being addressed with early-stage formal verification.
How to leverage a simpler, standardized approach to describing generic and reusable stimulus sequences for verification IP.
Finite State Machines are such a familiar part of design, we can forget how often they generate errors. Learn how to address them quickly and most efficiently
Using triple modular redundancy, error detection and correction, and ‘safe’ FSMs to ensure greater functional safety in FPGA-based designs
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