Many design teams are looking at ways in which they can make use of 3D integration. Here are eight requirements for an effective 3D-IC design flow.
A look at some of the design and physical verification challenges of working with finFET and FD-SOI devices, including their impact on layout, DRC and LVS.
The arrival of the 20nm and finFET-based sub-20nm processes bring with them challenges for custom IC design. These are the five key areas and a methodology that can address them.
2.5D-IC integration overcomes 2D limitations such as cost, offchip bandwidth bottlenecks and I/O pin scarcity, and offers a route to true 3D-IC integration.
- Expert Blog Building an RTL sign-off flow
- Expert Blog Better analysis helps improve design quality
- Article Physical verification of finFET and FD-SOI devices
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