March 18, 2024
Certification to ISO 26262 for automotive systems and compatibility with the latest Arm9 generation of processors and the CHI-E interface are among the updates to Arteris’ Ncore cache-coherent on-chip network IP framework.
March 14, 2024
Arm is working with Cadence and Siemens on separate projects to support its plans in the SDV space.
March 13, 2024
DVCon Europe is looking for papers to be presented at this year’s event in mid-October.
March 4, 2024
The board of directors of Accellera Systems Initiative has approved the 2023 edition of the Verilog-AMS standard for release.
February 22, 2024
Cadence has agreed to work with Intel Foundry Services on IP and flows for the 18A process, which will include backside power delivery and nanosheet transistors.
February 8, 2024
Accellera has formed a working group to look at extensions to SystemVerilog to improve support for mixed-signal designs.
February 1, 2024
Cadence has introduced a platform for performing thermal and thermal-stress analysis of subsystems, from 2.5D and 3DICs to PCBs and complete electronic assemblies.
January 21, 2024
A new paper looks at examples for using The Boundary Condition Independent Reduced Order Model (BCI-ROM) in its VHDL-AMS implementation for electro-thermal analysis.
January 12, 2024
Workshops on portable stimulus, functional safety, verification of RISC-V processors, and design with chiplets and large language models will feature at the upcoming 2024 DVCon US.
December 27, 2023
The two best papers at the recent DVCon Europe underlined two of the issues that now face chip-implementation teams: efficient flows and reliability.