Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
Doc Formal begins a two-part series by describing the solid and well-established foundations of formal verification.
CCIX is a cache coherency protocol, based on PCI Express, for interconnecting high-performance heterogenous multiprocessing systems.
Quadrupling the performance of a dedicated CNN engine within an embedded vision processing core brings more complex graph processing within reach.
Expert Insight Introducing Doc Formal: the journey so far
Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
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Expert Insight A reliability checklist for the Connected World
Reliability is growing to match security as a key challenge for PCB design. These tools and techniques will help you rise to it.
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Expert Insight Protecting content transmitted over USB Type-C connections
SoC developers who want to use USB Type-C in their designs will have to implement HDCP 2.2 content protection so that the target devices will be able to play protected content.
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Article Applying sub-threshold circuit techniques to IoT device design
Operating at near-threshold or sub-threshold voltages reduces static and dynamic power consumption, at the cost of design complexity.
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