Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
The verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
The basics of USB 3.2, how to implement it in an SoC, and how USB Type-C connectors and cables are used in USB 3.2 systems.
How the digital twin can fuel automotive verification flows impossible in the real world.
Expert Insight An open-source framework for greater flexibility in machine-learning development
Exchange frameworks are emerging to make it easier for neural-network developers to swap between development environments.
- Article How Starblaze combined simulation and emulation to design SSD controller firmware
- Expert Insight EUV’s arrival demands a new resolution enhancement flow
Article Tackling the design challenges of PCIe 5.0
Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.
- Article How Channel Operating Margin helps Gigabit Ethernet PCB analysis
- Expert Insight The Wally Rhines interview – Part Two: AI, automotive and security
The antifuse advantage for one-time programmable non-volatile memory
Antifuse-based OTP NVM is highly scalable, has the area efficiency to enable macros of megabit capacities, and offers low read power.
- Expert Insight Why AI needs security
- Article Using threat models and risk assessments to define device security requirements
Expert Insight Flexible embedded vision processing architectures for machine-learning applications
Machine-learning strategies for embedded vision are evolving so quickly that designers need access to flexible, heterogenous processor architectures that can adapt as the algorithms evolve.
- Article Managing the evolving architecture of integrated ADAS controllers
- Article Bringing Ethernet time-sensitive networking to automotive applications
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