Latest
Reliability verification: It’s all about the baseline
How you can use the dedicated rule decks now being provided by foundries as the foundation for a reliability verification flow.-
How to improve throughput for gate-level simulation
How Starblaze combined simulation and emulation to design SSD controller firmware
Slash test time by combining hierarchical DFT and channel sharing
Guides
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Portable stimulus
Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
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Dynamic power optimization
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
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Monolithic 3DIC for SoC
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
Expert Insights
Why AI needs security
As AI becomes pervasive in computing applications, so too does the need for high-grade security in all levels of the system.
An open-source framework for greater flexibility in machine-learning development
Exchange frameworks are emerging to make it easier for neural-network developers to swap between development environments.
Flexible embedded vision processing architectures for machine-learning applications
Machine-learning strategies for embedded vision are evolving so quickly that designers need access to flexible, heterogenous processor architectures that can adapt as the algorithms evolve.
EDA
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Expert Insight EUV’s arrival demands a new resolution enhancement flow
Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.
- Expert Insight Doc Formal: Achieving exhaustive formal verification of packet-based designs
- Expert Insight Managing waivers in reliability verification
PCB
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Article Tackling the design challenges of PCIe 5.0
Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.
- Article How Channel Operating Margin helps Gigabit Ethernet PCB analysis
- Expert Insight The Wally Rhines interview – Part Two: AI, automotive and security
IP
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Article Using threat models and risk assessments to define device security requirements
The proliferation of attacks against embedded systems is making designers realize that they need to do more to secure their products and ecosystems.
- Article Managing the evolving architecture of integrated ADAS controllers
- Expert Insight Picking the right-sized crypto processor for your SoC
Embedded
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Article Bringing Ethernet time-sensitive networking to automotive applications
An evolution of the Ethernet standard enable time-sensitive networking with the predictable latencies and guaranteed bandwidth necessary for automotive applications.
- Expert Insight How emulation’s SoC and SoS advantages begin with transaction-based co-modeling
- Expert Insight The impact of AI on autonomous vehicles
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