Clock-tree generation is coming under increased scrutiny because of its role in dynamic power consumption and problems caused by on-chip PVT variation.
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
Dynamic voltage and frequency scaling is effective for low-power VLSI design. Body or back bias can provide additional control over leakage and performance.
Sequential equivalence checking can help trap errors introduced by clock gate insertion, uninitialised registers, and X propagation issues.
These days, when it comes to innovation: The car's the star - not the stooge.
How to accelerate many aspects of software testing by using virtual prototypes to stand in for target hardware from early in the development cycle.
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A look at three design challenges for USB Type-C: implementing two SuperSpeed datapaths on a reversible connector; partitioning the design to support multiple USB Type-C variants; and partitioning the management software.
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A quick look at Bluetooth Smart and how it can be used to provide network connections in certain classes of IoT application.
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A look at using end-to-end prototyping to ease architecture development, hardware/software integration, and system validation in SoC designs
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