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    Article How lithography simulations enable silicon photonics

    Precise curved geometries are vital to making this emerging and cost-effective CMOS-based technology work. This primer explains its advantages and how litho tools are evolving to meet the challenges it presents.

  2. Article Overcoming complex CDC violations with a concurrent block and SoC-level verification flow
  3. Article Using formal techniques to help tackle SoC verification challenges


  1. Bundles help group signals on package pinouts
    Article Multi-fabric planning for more efficient PCB design

    A coordinated design methodology fine-tunes chip-to-package PCB layout and routing that involves high-integration devices.

  2. Article The future of thermal simulation for electronics products
  3. Article Zeroing in on the problems of fast board-level interconnect


  1. Pattern matching DRC featured image
    Article How to use pattern matching to improve automatic waiver management

    Fab and IP vendor collaboration is making pattern matching-based libraries a vital component of DRC accuracy and efficiency. Learn how to take advantage.

  2. Article Enabling symmetric multiprocessing for embedded Linux on ARC processor cores
  3. Article Accelerating ‘time to prototype’ with ProtoCompiler


  1. Dr Lauro Rizzatti is an independent verification consultant. You can contact him at lauro AT rizzatti DOT com
    Expert Insight The budget case for emulation

    Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’

  2. Article Hybrid emulation for development, validation and verification
  3. Article The evolution of software debug using hardware emulators



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