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IP based design with Synplify - featimg

Getting the most out of IP based FPGA design with Synplify

How Synplify makes it easier to use IP in FPGA-based designs, and package your own IP for secure reuse, on Altera and Xilinx devices

Guides

  • 20nm

    EDA - Technologies

    The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.

  • Parasitic extraction

    EDA - Techniques

    Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.

  • DVFS and body bias

    EDA - Technologies

    Dynamic voltage and frequency scaling is effective for low-power VLSI design. Body or back bias can provide additional control over leakage and performance.

Expert Insights

Pranav Ashar

DO-254 without tears

Pranav Ashar

Compliance with aviation’s hardware design standard is seen as a ‘tough ask’, but EDA’s own evolution has made that process easier than you may think.

Marco Casale-Rossi

Automotive ICs drive advanced design at established nodes

Designers working on automotive ICs, to be built on established processes, can benefit from the power of design tools developed for advanced processes.

Dunstan Power

Assessing technical design trade-offs during product development

Understanding design trade-offs can help achieve the correct balance of functionality, cost, and time to market, says design consultancy chief

EDA

  1. Veloce2 emulator
    Article Assertion-based emulation

    Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.

  2. Article Overcoming complex CDC violations with a concurrent block and SoC-level verification flow
  3. Article Using formal techniques to help tackle SoC verification challenges

PCB

  1. Bundles help group signals on package pinouts
    Article Multi-fabric planning for more efficient PCB design

    A coordinated design methodology fine-tunes chip-to-package PCB layout and routing that involves high-integration devices.

  2. Article The future of thermal simulation for electronics products
  3. Article Zeroing in on the problems of fast board-level interconnect

IP

  1. Expert Insight - Holisitic approach to IoT chip design_feat img.jpg
    Expert Insight A holistic approach to IoT chip design

    A look at the challenges of designing chips for the Internet of Things, or IoT, and some of the responses to those challenges

  2. Article How to use pattern matching to improve automatic waiver management
  3. Article Enabling symmetric multiprocessing for embedded Linux on ARC processor cores

Embedded

  1. Dr Lauro Rizzatti is an independent verification consultant. You can contact him at lauro AT rizzatti DOT com
    Expert Insight The budget case for emulation

    Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’

  2. Article Accelerating ‘time to prototype’ with ProtoCompiler
  3. Article Hybrid emulation for development, validation and verification

Briefing

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