The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.
Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.
Dynamic voltage and frequency scaling is effective for low-power VLSI design. Body or back bias can provide additional control over leakage and performance.
Sign-off lithography verification is vital as we move beyond double to multi-patterning but changing responsibilities in the flow must be handed with care.
FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.
Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
Expert Insight Rethinking SoC verification
The argument for an integrated approach to SoC verification
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Article The future of thermal simulation for electronics products
Complexity and the increasing use of thermal analysis software by non-expert designers demands new approaches for chip and PCB implementations.
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Article Using Ethernet in automotive networks
Will Ethernet become the dominant interconnect for automotive applications? A look at the market trends and standards, and how to use Ethernet IP and virtual-prototyping solutions in automotive applications.
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Expert Insight Prototypers get faster route to first clock tick
ProtoCompiler understands HAPS FPGA prototyping hardware, so it can optimize logic placement and partitioning, even on designs with up to 250m ASIC gates.
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