Latest

EDA

  1. Moores Cores - featimg
    Article Using optimized design flows to meet PPA goals for SoC processor cores

    How tuning a design flow can help optimize SoC processor cores for power, performance and area – and make it possible to do different optimisations for different cores on the same SoC.

  2. Article Exploiting Verific tools and features at the right abstraction level
  3. Expert Insight Six key criteria for deciding to migrate to a finFET process

PCB

  1. Bundles help group signals on package pinouts
    Article Multi-fabric planning for more efficient PCB design

    A coordinated design methodology fine-tunes chip-to-package PCB layout and routing that involves high-integration devices.

  2. Article The future of thermal simulation for electronics products
  3. Article Zeroing in on the problems of fast board-level interconnect

IP

  1. Steven Cline is a senior design automation Manager at Altera’s Austin Technology Center, focusing on design-flow automation for traditionally placed and routed blocks and custom FPGA IP used on Altera’s advanced FPGA products.
    Expert Insight Using standardized design flows to cut time to tape-out – and speed design-flow evolution

    Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out – and speed the evolution of its design flows.

  2. Article Using Ethernet in automotive networks
  3. Article How to use PCI Express in low-power mobile SoCs by exploiting M-PCIe

Embedded

  1. ZeBu server
    Article Hybrid emulation for development, validation and verification

    This article introduces hybrid emulation, a combination of emulation and virtual prototypes, and its application to tasks such as architecture validation, early software development and software-driven verification.

  2. Article The evolution of software debug using hardware emulators
  3. Expert Insight Prototypers get faster route to first clock tick

Briefing

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