Latest
Slash test time by combining hierarchical DFT and channel sharing
A hierarchical methodology removes DFT from the critical path for large designs. The methodology is compatible with other techniques such as channel sharing, which can further reduce ATPG turn-around time and test cost.-
Layout-database file control: the missing link
Extend formal property verification to protocol-driven datapaths
The three critical data validation points in a design flow
Guides
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Portable stimulus
Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
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Dynamic power optimization
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
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Monolithic 3DIC for SoC
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
Expert Insights
Formal fundamentals: what’s hiding behind your constraints
Effective formal verification demands striking a careful balance in the use of constraints – too many slows things down, but too few may let bugs slip through.
Picking the right-sized crypto processor for your SoC
Choosing the right crypto processor implementation involves a complex set of design tradeoffs between speed, area, power consumption and flexibility. Using consistent benchmarks can help explore your options.
Power analysis isn’t just for battery-operated products
Andy Ladd highlights the wide range of peak-power concerns around plugged-in devices.
EDA
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Article Formal fault analysis for ISO 26262: Find faults before they find you
How to use formal fault pruning, injection and sequential equivalency checking to meet the FMEA analysis requirements of the functional safety standard.
- Expert Insight How emulation’s SoC and SoS advantages begin with transaction-based co-modeling
- Expert Insight Doc Formal: Harness the power of invariant-based bug hunting
PCB
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Article Tackling the design challenges of PCIe 5.0
Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.
- Article How Channel Operating Margin helps Gigabit Ethernet PCB analysis
- Expert Insight The Wally Rhines interview – Part Two: AI, automotive and security
IP
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Article Bringing Ethernet time-sensitive networking to automotive applications
An evolution of the Ethernet standard enable time-sensitive networking with the predictable latencies and guaranteed bandwidth necessary for automotive applications.
- Expert Insight The impact of AI on autonomous vehicles
- Expert Insight How eFPGAs will help build the brave new world of AI
Embedded
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Article Keeping up with the bandwidth demands of embedded displays
Increasing resolutions and rising frame rates are making it more challenging than ever to drive embedded displays effectively.
- Article Driving 4K smartphone and AR/VR device displays
- Expert Insight Optimizing power and performance trade-offs in CNN implementations for embedded vision
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