Latest

Bundles help group signals on package pinouts

Multi-fabric planning for more efficient PCB design

A coordinated design methodology fine-tunes chip-to-package PCB layout and routing that involves high-integration devices.

Guides

  • 20nm

    EDA - Technologies

    The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.

  • Parasitic extraction

    EDA - Techniques

    Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.

  • DVFS and body bias

    EDA - Technologies

    Dynamic voltage and frequency scaling is effective for low-power VLSI design. Body or back bias can provide additional control over leakage and performance.

Expert Insights

Steve Cline

Using standardized design flows to cut time to tape-out – and speed design-flow evolution

Steven Cline is a senior design automation Manager at Altera’s Austin Technology Center, focusing on design-flow automation for traditionally placed and routed blocks and custom FPGA IP used on Altera’s advanced FPGA products.

Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.

Rebecca Lipon

Rethinking SoC verification

The argument for an integrated approach to SoC verification

Pranav Ashar

It’s time to embrace objective-driven verification

How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.

EDA

  1. Future of thermal simulation
    Article The future of thermal simulation for electronics products

    Complexity and the increasing use of thermal analysis software by non-expert designers demands new approaches for chip and PCB implementations.

  2. Article How to use PCI Express in low-power mobile SoCs by exploiting M-PCIe
  3. Guide Monolithic 3DIC for SoC

PCB

  1. High-speed I/O eye diagram - thumbnail
    Article Zeroing in on the problems of fast board-level interconnect

    A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.

  2. Expert Insight Straighten up and fly right
  3. Expert Insight Make best-practice lean NPI for PCB a reality

IP

  1. Car cutaway
    Article Using Ethernet in automotive networks

    Will Ethernet become the dominant interconnect for automotive applications? A look at the market trends and standards, and how to use Ethernet IP and virtual-prototyping solutions in automotive applications.

  2. Guide Hardware trojan attacks and countermeasures
  3. Guide On-chip clock strategies and GALS

Embedded

  1. Mick Posner is Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions.
    Expert Insight Prototypers get faster route to first clock tick

    ProtoCompiler understands HAPS FPGA prototyping hardware, so it can optimize logic placement and partitioning, even on designs with up to 250m ASIC gates.

  2. Expert Insight Bringing true power analysis to hardware/software co-design
  3. Article Debugging with virtual prototypes – Part Four

Briefing

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