Latest

Mixed-signal verification of advanced SoCs using VCS AMS

How ST Microelectronics uses Synopsys' VCS AMS, combining VCS functional verification and CustomSim, to verify one of its mixed-signal designs

Assertion-based emulation

Topics: IP - Design Management, EDA - IC Implementation, Embedded - Integration & Debug, EDA - Verification
Acceleration homes in on power issues

Topics: EDA - ESL, Verification
A short introduction to IC Compiler II

Topics: EDA - IC Implementation Comments Off

Guides

20nm

EDA - Technologies
The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.
Parasitic extraction

EDA - Techniques
Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.
DVFS and body bias

EDA - Technologies
Dynamic voltage and frequency scaling is effective for low-power VLSI design. Body or back bias can provide additional control over leakage and performance.

Expert Insights

Dunstan Power

Assessing technical design trade-offs during product development

Understanding design trade-offs can help achieve the correct balance of functionality, cost, and time to market, says design consultancy chief

Sarath Kirihennedige

Taking control of constraints verification

Constraints are a vital part of IC design, yet the management and verification of constraints’ quality, completeness, consistency and fidelity to the designer’s intent is an evolving art.

Ron Lowman

A holistic approach to IoT chip design

A look at the challenges of designing chips for the Internet of Things, or IoT, and some of the responses to those challenges

EDA

Article How lithography simulations enable silicon photonics
Precise curved geometries are vital to making this emerging and cost-effective CMOS-based technology work. This primer explains its advantages and how litho tools are evolving to meet the challenges it presents.
Article Overcoming complex CDC violations with a concurrent block and SoC-level verification flow
Article Using formal techniques to help tackle SoC verification challenges

PCB

Article Multi-fabric planning for more efficient PCB design
A coordinated design methodology fine-tunes chip-to-package PCB layout and routing that involves high-integration devices.
Article The future of thermal simulation for electronics products
Article Zeroing in on the problems of fast board-level interconnect

IP

Article How to use pattern matching to improve automatic waiver management
Fab and IP vendor collaboration is making pattern matching-based libraries a vital component of DRC accuracy and efficiency. Learn how to take advantage.
Article Enabling symmetric multiprocessing for embedded Linux on ARC processor cores
Article Accelerating ‘time to prototype’ with ProtoCompiler

Embedded

Expert Insight The budget case for emulation
Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’
Article Hybrid emulation for development, validation and verification
Article The evolution of software debug using hardware emulators

Briefing

January 28, 2015

Cadence updates Sigrity tools and license options

Cadence Design Systems has added LPDDR4 support and a topology explorer to its Sigrity lineup for signal and power integrity analysis of PCB-based designs, as well as more flexible licensing options.

January 27, 2015

ARM to provide safety docs for real-time processors

ARM has picked up TÜV Süd certification for a version of its C compiler and produced an ISO 26262 documentation pack for the Cortex-R5 processor

January 19, 2015

Ambiq uses subthreshold techniques to cut power on ARM MCUs

Research by the University of Michigan into subthreshold circuit design has led to spinoff company Ambiq Micro creating a family of microcontrollers that it claims provide an ARM Cortex-M4F with power consumption at levels normally associated with an M0+.

January 14, 2015