Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
A static-analysis tool that checks for errors in HDL code, lint is becoming an increasingly important addition to simulation for RTL and SoC signoff.
Emulators have come a long way since their first introduction nearly three decades ago.
To verify large, complex designs and meet time-to-market, you must use both simulation and emulation.
A look at the ways in which the I2C serial interface specification is being updated to form I3C, and its use in sensor subsystems
Expert Insight Are you formally secure?
A look at how formal verification strategies can be used to check the security feature of complex SoCs for potential data leakage and data integrity issues
- Expert Insight Comparing your design to itself – a crucial part of verification
- Article Implementing USB Type-C
Expert Insight Where tools end and best practices begin
Learn how you can benchmark your design practices against the most successful players in the PCB market – and why you should.
- Article PCB tool innovation from the middle out
- Article Simulation predicts performance of automotive Ethernet
Article True random number generators for a more secure IoT
An analysis of what it takes to build true random number generators that can provide a strong cryptographic basis for systems security, especially for IoT devices.
- Expert Insight Enabling energy-efficient wireless IoT designs with Bluetooth Smart IP
- Article What’s cooking at the Flash Diner?
Expert Insight Laying the foundations of a more secure IoT
The challenges of creating a more secure IoT, and the role that hardware roots of trust can play in doing so.
- Expert Insight Still using Moore’s Law to beat up on the automotive industry?
- Article Accelerating Android bring-up using VDKs in the LAVA framework
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