Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
Artificial intelligence and machine learning require the performance and flexibility offered by embedded FPGA (eFPGA) technology.
Insights from research into reliability at Imec led to self-learning chips, security technologies, and finFET biosensors.
Ashish Darbari sets out the fundamental qualities of a successful formal verification project.
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3D integration technology has split into a number of different approaches, each of which brings a different combination of benefits in terms of performance.
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Expert Insight Bringing AI into our lives
Using specialised processors to implement key AI computation tasks such as CNNs.
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