Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
A static-analysis tool that checks for errors in HDL code, lint is becoming an increasingly important addition to simulation for RTL and SoC signoff.
Mentor's chairman and CEO has dug into why chip sales forecasts often miss the target and suggests some tools for assessing the Internet of Things.
Analysts say there is a $1B market on the horizon. We talk with Mentor's Jean-Marie Brunet about where such a number could come from.
Users now demand a smooth GUI experience. Making sure they get one requires harvesting and understanding key metrics.
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Engineers developing an SoC for the automotive market have to show that it doesn’t have functional safety issues – even if the SoC enters an unexpected state. Here’s how to tackle the safety verification task.
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Expert Insight Where tools end and best practices begin
Learn how you can benchmark your design practices against the most successful players in the PCB market – and why you should.
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Expert Insight A vision of autonomous driving
Enabling autonomous driving will demand embedded processors that can process multiple HD video streams and analyse them using convolutional neural networks.
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Expert Insight The emulator thrives as verification models mushroom
Emulators have come a long way since their first introduction nearly three decades ago.
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