Latest

vpdebug2thumb

Debugging with virtual prototypes – part two

The second part of our series illustrates VP tools and techniques through the familiar example of Linux bring-up on an ARM-based SoC.

Guides

  • X propagation

    EDA - Techniques

    X propagation within RTL simulations can hide fatal bugs. Uncovering and eliminating the effect improves design quality and avoids respins.

  • On-chip variation (OCV)

    EDA - Techniques

    Accounting for on-chip variation (OCV) has become a critical factor in assuring timing closure for nanometer-scale ICs and avoiding over-pessimistic margins.

  • System virtual prototyping

    EDA - Techniques

    The technique enables early software development and hardware/software co-design strategies before a project is more rigidly defined in RTL.

Expert Insights

Carey Robertson

FinFET parasitics come under control

Carey Robertson is a director of product marketing at Mentor Graphics overseeing the marketing activities for layout versus schematic (LVS) and extraction products.

Extracting finFET parasitics means a shift to 3D models, field solvers for greater accuracy, and MCMM techniques.

David Fried

Lithography challenges threaten the cost benefits of IC scaling

The costs of advanced lithography techniques at 1xnm, and the yield and reliability risks from the resultant process variation, will stop many companies getting the typical economic advantages of scaling.

Brian Fuller

Goodbye to the mixed-signal black box

In pursuit of better design methodologies coupled with shrinking design-cycles, real-number modeling is emerging as a smart verification choice.

EDA

  1. Jack Erickson is director of product management at Cadence Design Systems.
    Expert Insight Slow winter or new spring for hardware design?

    Problems with process scaling make it seem as though the long era of innovative, lucrative hardware design is coming to an end. But is that really the case?

  2. Article How high-level synthesis helps optimize low power designs – Part One
  3. Expert Insight The requirements for complete RTL signoff

PCB

  1. Richard Goering, senior manager of technical communications, Cadence
    Expert Insight IPC-2581 transfer standard gains momentum

    Forty six companies have joined the consortium developing the increasingly important IPC-2581 data transfer standard for PCB designs.

  2. Article Keeping high-speed designs clean with ERC
  3. Expert Insight Focus on product creation for effective design

IP

  1. Hybrid memory cube architecture
    Article DRAM interfaces for mobile and networking designs

    Mobile and networking platforms need high bandwidth, low power consumption, and small footprint. These needs drove standards, such as LPDDR4, Wide I/O 2 and Hybrid Memory Cube.

  2. Article Accelerating process migration in advanced ASIC design at Bull
  3. Article Why use USB 3.0?

Embedded

  1. embeddebug_feat img
    Article Debugging with virtual prototypes – part one

    The first in a series of articles about using virtual prototyping techniques to achieve more effective debug.

  2. Expert Insight Real-world multicore embedded systems: review
  3. Article Knock down the wall to SoC integration

Briefing

PLATINUM SPONSORS

Mentor Graphics GLOBALFOUNDRIES Synopsys Samsung Semiconductor Cadence Design Systems
View All Sponsors