Clock-tree generation is coming under increased scrutiny because of its role in dynamic power consumption and problems caused by on-chip PVT variation.
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
Dynamic voltage and frequency scaling is effective for low-power VLSI design. Body or back bias can provide additional control over leakage and performance.
The introduction of bigger FPGAs enables more complex prototypes - but makes debugging more of a challenge. Here's one way to address the issue.
A look at the USB Type-C connector and the enhanced data rates and charging facilities it will enable
What hardware designers can learn from software verification techniques such as agile, behaviour-driven development, code coverage and zero known defect strategies
Article Simulation predicts performance of automotive Ethernet
Ethernet is set to become one of the key communications standards for automotive. Early system-level simulation lets designers gauge performance before moving to hardware prototypes.
- Article Eight steps for efficient PCB manufacturing and assembly – Part Two
- Article Eight steps for efficient PCB manufacturing and assembly – Part One
Article Fixing late ECOs in ARM core subsystems at STMicroelectronics
Using equivalence checking to validate ECOs in ARM core subsystem development at STMicroelectronics
- Article Developing and integrating configurable GPU IP using FPGA-based prototyping
- Expert Insight Neural networks bring advanced object detection to embedded vision
Article Handling power dropouts in MSP430 energy-harvesting designs
Software for energy-harvesting designs needs to cope with sudden power failures. FRAM storage can reduce the power and performance penalties of full resets.
- Article Cortex-A72: microarchitecture tweaks focus on efficiency
- Expert Insight Design reaches out from the edge
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