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The evolution of software debug using hardware emulation

The evolution of software debug using hardware emulators

We look at how best to leverage both software debug tools and emulators, the limitations to traditional techniques, and the drive toward offline debug.

Guides

  • 20nm

    EDA - Technologies

    The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.

  • Parasitic extraction

    EDA - Techniques

    Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.

  • DVFS and body bias

    EDA - Technologies

    Dynamic voltage and frequency scaling is effective for low-power VLSI design. Body or back bias can provide additional control over leakage and performance.

Expert Insights

Rebecca Lipon

Rethinking SoC verification

Rebecca Lipon is the senior product marketing manager for the functional verification product line at Synopsys. Prior to joining the marketing team, Rebecca was an applications engineer at Synopsys working on UVM/VMM adoption, VCS, VIP, static and formal verification deployments.

The argument for an integrated approach to SoC verification

Pranav Ashar

It’s time to embrace objective-driven verification

How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.

Mick Posner

Prototypers get faster route to first clock tick

ProtoCompiler understands HAPS FPGA prototyping hardware, so it can optimize logic placement and partitioning, even on designs with up to 250m ASIC gates.

EDA

  1. Future of thermal simulation
    Article The future of thermal simulation for electronics products

    Complexity and the increasing use of thermal analysis software by non-expert designers demands new approaches for chip and PCB implementations.

  2. Article How to use PCI Express in low-power mobile SoCs by exploiting M-PCIe
  3. Guide Monolithic 3DIC for SoC

PCB

  1. High-speed I/O eye diagram - thumbnail
    Article Zeroing in on the problems of fast board-level interconnect

    A panel session at DAC 2014 focused on the problems of high-speed, board-level interconnect and the roles of codesign and power integrity in solving them.

  2. Expert Insight Straighten up and fly right
  3. Expert Insight Make best-practice lean NPI for PCB a reality

IP

  1. Dopant-level trojan standard cell developed by Georg Becker and coworkers
    Guide Hardware trojan attacks and countermeasures

    IC designers are becoming increasingly worried about the possibility of third parties inserting malicious ‘trojan’ circuitry into their ICs.

  2. Guide On-chip clock strategies and GALS
  3. Expert Insight Protecting IP in a collaborative signoff environment

Embedded

  1. Bill Neifert is chief technology officer of Carbon Design Systems. Bill has designed high-performance verification and system integration solutions, and also developed an architecture and coding style for high-performance RTL simulation in C/C++.
    Expert Insight Bringing true power analysis to hardware/software co-design

    While some HW/SW co-design and verification techniques are in place, a power analysis methodology is only just emerging

  2. Article Debugging with virtual prototypes – Part Four
  3. Expert Insight Power management in embedded systems – new thinking required

Briefing

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