Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
Using specialised processors to implement key AI computation tasks such as CNNs.
If we thought about verfication-for-security in a different way, the Spectre and Meltdown vulnerabilities could well have been avoided.
Ashish Darbari concludes his series on the need for new verification strategies by considering Debug and Signoff & Review.
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