Latest
Fast, accurate layout merging for SoC flows
How to achieve efficient merging of data from formats such as OASIS, GDS, and OpenAccess to ensure timely verification through DRC runs.-
Low-power debugging made easy
A better way to manage error reporting at the chip and block levels
Create more flexible virtual sequences with Portable Stimulus
Guides
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Portable stimulus
Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
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Dynamic power optimization
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
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Monolithic 3DIC for SoC
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
Expert Insights
Emulation for AI: Part Two
The second part of this feature looks at how Wave Computing's objectives with its dataflow processing unit for AI mapped to the use of emulation in its development.
Emulation for AI: Part One
An increasing number of AI players are building their own silicon and finding that emulation is key to overcoming the major challenges.
Doc Formal: Introducing the ADEPT FV flow
Escape formal's narrower definitions with a flow that shows you how to Avoid, Detect, Erase, Prove Absence and Tape Out while avoiding bugs.
EDA
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Article Enhanced model-based hinting may be the edge you need below 20nm
A detailed dive into how MBH strategies for litho hotspots have been enhanced to deal with double patterning at 20nm and below.
- Article Win on the fault campaign trail with formal
- Expert Insight Verifying clock domain crossings in UPF-based low-power SoCs
PCB
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Article Tackling the design challenges of PCIe 5.0
Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.
- Article How Channel Operating Margin helps Gigabit Ethernet PCB analysis
- Expert Insight The Wally Rhines interview – Part Two: AI, automotive and security
IP
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Article Optimizing the hardware implementation of machine learning algorithms
Optimizing the way in which machine learning algorithms are implemented in hardware will be a major differentiator for SoCs, especially for edge devices.
- Article The antifuse advantage for one-time programmable non-volatile memory
- Expert Insight Understanding USB 3.2 and Type-C
Embedded
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Article Using threat models and risk assessments to define device security requirements
The proliferation of attacks against embedded systems is making designers realize that they need to do more to secure their products and ecosystems.
- Expert Insight An open-source framework for greater flexibility in machine-learning development
- Expert Insight Flexible embedded vision processing architectures for machine-learning applications
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