The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.
Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.
Dynamic voltage and frequency scaling is effective for low-power VLSI design. Body or back bias can provide additional control over leakage and performance.
Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
Sign-off lithography verification is vital as we move beyond double to multi-patterning but changing responsibilities in the flow must be handed with care.
FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.
Article Hybrid emulation for development, validation and verification
This article introduces hybrid emulation, a combination of emulation and virtual prototypes, and its application to tasks such as architecture validation, early software development and software-driven verification.
- Expert Insight Using standardized design flows to cut time to tape-out – and speed design-flow evolution
- Article When failure is not an option in automotive verification
Article The future of thermal simulation for electronics products
Complexity and the increasing use of thermal analysis software by non-expert designers demands new approaches for chip and PCB implementations.
- Article Zeroing in on the problems of fast board-level interconnect
- Expert Insight Straighten up and fly right
Article Using Ethernet in automotive networks
Will Ethernet become the dominant interconnect for automotive applications? A look at the market trends and standards, and how to use Ethernet IP and virtual-prototyping solutions in automotive applications.
- Article How to use PCI Express in low-power mobile SoCs by exploiting M-PCIe
- Guide Hardware trojan attacks and countermeasures
Expert Insight Prototypers get faster route to first clock tick
ProtoCompiler understands HAPS FPGA prototyping hardware, so it can optimize logic placement and partitioning, even on designs with up to 250m ASIC gates.
- Expert Insight Bringing true power analysis to hardware/software co-design
- Article Debugging with virtual prototypes – Part Four
View All Sponsors