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Visual: cars speeding along a road

Managing the evolving architecture of integrated ADAS controllers

Designers need to understand how the architecture of electronic control units used to implement ADAS in vehicles is changing.

Guides

  • Portable stimulus

    EDA - Standards, Technologies

    Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.

  • Dynamic power optimization

    EDA - Techniques

    FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.

  • Monolithic 3DIC for SoC

    EDA - Technologies

    Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.

Expert Insights

Ashish Darbari

Doc Formal: Achieving exhaustive formal verification of packet-based designs

Ashish Darbari is CEO of formal verification consultancy Axiomise.

Ashish Darbari breaks down formal's value to this challenging verification task with code examples and reference to VC Formal from Synopsys.

Dina Medhat

Managing waivers in reliability verification

Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.

Ashish Darbari

The budget case for formal verification

Doc Formal sets out the 10 cost points in verification that formal will help you control and reduce.

EDA

  1. Sean Safarpour is the Director of Application Engineering at Synopsys.
    Expert Insight Formal fundamentals: what’s hiding behind your constraints

    Effective formal verification demands striking a careful balance in the use of constraints – too many slows things down, but too few may let bugs slip through.

  2. Article Formal fault analysis for ISO 26262: Find faults before they find you
  3. Expert Insight Power analysis isn’t just for battery-operated products

PCB

  1. PCI_Express_logo
    Article Tackling the design challenges of PCIe 5.0

    Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.

  2. Article How Channel Operating Margin helps Gigabit Ethernet PCB analysis
  3. Expert Insight The Wally Rhines interview – Part Two: AI, automotive and security

IP

  1. Ruud Derwig has more than 20 years of experience with software and system architectures for embedded systems. Key areas of expertise include (real-time, multi-core) operating systems, media processing, component based architectures, and security. He holds a master's degree in computing science and a professional doctorate in engineering. Derwig is currently a software and systems architect at Synopsys.
    Expert Insight Picking the right-sized crypto processor for your SoC

    Choosing the right crypto processor implementation involves a complex set of design tradeoffs between speed, area, power consumption and flexibility. Using consistent benchmarks can help explore your options.

  2. Article Bringing Ethernet time-sensitive networking to automotive applications
  3. Expert Insight The impact of AI on autonomous vehicles

Embedded

  1. Expert Insight How emulation’s SoC and SoS advantages begin with transaction-based co-modeling

    An introduction to how virtual emulation has fueled the application of co-modeling for complex design verification.

  2. Expert Insight How eFPGAs will help build the brave new world of AI
  3. Article Keeping up with the bandwidth demands of embedded displays

Briefing

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