The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.
Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.
Dynamic voltage and frequency scaling is effective for low-power VLSI design. Body or back bias can provide additional control over leakage and performance.
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FInFET memories have different defects than those based on planar transistors. Here's how to test and repair them.
Lint is no longer just about checking RTL code. It already incorporates functional verification within a three-stage analysis. Time to look again at a 'familiar' technology.
Article How to use pattern matching to improve automatic waiver management
Fab and IP vendor collaboration is making pattern matching-based libraries a vital component of DRC accuracy and efficiency. Learn how to take advantage.
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Article Multi-fabric planning for more efficient PCB design
A coordinated design methodology fine-tunes chip-to-package PCB layout and routing that involves high-integration devices.
- Article The future of thermal simulation for electronics products
- Article Zeroing in on the problems of fast board-level interconnect
Expert Insight Six key criteria for deciding to migrate to a finFET process
Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages
- Expert Insight Using standardized design flows to cut time to tape-out – and speed design-flow evolution
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Article Hybrid emulation for development, validation and verification
This article introduces hybrid emulation, a combination of emulation and virtual prototypes, and its application to tasks such as architecture validation, early software development and software-driven verification.
- Article The evolution of software debug using hardware emulators
- Expert Insight Prototypers get faster route to first clock tick
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