Latest

Synopsys VCS Xprop feat

Catching X-propagation related issues at RTL

Catching x-propagation issues at RTL saves time and reduces uncertainty in gate-level verification

Guides

  • Interconnect resistance

    EDA - Techniques

    A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.

  • Cell pin access

    EDA - Techniques

    Increasingly complex design rules in 14nm and 16nm makes it harder to connect local routing to the inputs and outputs (pins) of standard cells.

  • X propagation

    EDA - Techniques

    X propagation within RTL simulations can hide fatal bugs. Uncovering and eliminating the effect improves design quality and avoids respins.

Expert Insights

Richard Goering

Henny Youngman’s advice to PCB designers

Richard Goering, senior manager of technical communications, Cadence

In a standing-room-only talk at the recent DesignCon conference, Eric Bogatin explained why comedian Henny Youngman could help them with signal integrity on PCBs.

Warren Stapleton

Next wave of innovation in verification technology must come from integration

The next boost to verification productivity will come from the integration of multiple strategies and tools.

Lisa Piper

Complexity drives smart reporting

Increasingly complex state machines are driving the need for smarter ways of reporting errors such as deadlocks and unreachable code in the source RTL.

EDA

  1. Mark Bollar is a product marketing director at Synopsys overseeing physical implementation.
    Expert Insight The new landscape of advanced design

    Advanced tools are being applied to established nodes to produce advanced designs for volume markets.

  2. Expert Insight Concurrency tackles MCMM issues head-on
  3. Article Debugging with virtual prototypes – Part Four

PCB

  1. Richard Goering, senior manager of technical communications, Cadence
    Expert Insight IPC-2581 transfer standard gains momentum

    Forty six companies have joined the consortium developing the increasingly important IPC-2581 data transfer standard for PCB designs.

  2. Article Keeping high-speed designs clean with ERC
  3. Expert Insight Focus on product creation for effective design

IP

  1. Neil Songcuan is a senior product marketing manager, responsible for the FPGA-based Prototyping Solution at Synopsys.
    Expert Insight Using HAPS to streamline IP to SoC integration

    The HAPS prototyping system can help designers integrate IP into SoCs more quickly.

  2. Expert Insight Consistency key to gaining the advantages of IP integration
  3. Article FPGA-based prototyping to validate the integration of IP into an SoC

Embedded

  1. Colin Walls
    Expert Insight Power management in embedded systems – new thinking required

    Effective low-power design for embedded-systems will take a new culture of close collaboration between hardware and software engineers.

  2. Article Debugging with virtual prototypes – Part Two
  3. Article Debugging with virtual prototypes – Part One

Briefing

PLATINUM SPONSORS

Mentor Graphics GLOBALFOUNDRIES Synopsys Samsung Semiconductor Cadence Design Systems
View All Sponsors