Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
SoC developers who want to use USB Type-C in their designs will have to implement HDCP 2.2 content protection so that the target devices will be able to play protected content.
German consultancy E-Cooling describes its strategy for thermal and airflow analysis.
The increasing complexity of human-machine interfaces is challenging processor designers to produce the necessary performance within a limited power budget
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Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
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