Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
A static-analysis tool that checks for errors in HDL code, lint is becoming an increasingly important addition to simulation for RTL and SoC signoff.
Our new columnist introduces himself and traces the progress of formal verification over the last two decades. Join the discussion.
This second part looks at Mentor's views on flow neutrality, how DRS360 was born, machine learning and the threat from embedded Trojans.
The rising bandwidth demands of data centres have driven the development of 25G Ethernet, which will also form a pathway to 100G.
Expert Insight The Wally Rhines interview – Part One: Mentor as a Siemens business
Our extended fireside chat with Mentor Chairman and CEO Wally Rhines begins by canvassing his thoughts now the Siemens deal is done.
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SSD controllers are becoming increasingly complex and as a result emulation is now the first choice for SSD verification. But your strategy must still meet five key criteria.
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