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Virtual sequences with portable stimulus - featured image.

Create more flexible virtual sequences with Portable Stimulus

Virtual sequences are considered challenging to write and re-use. Learn how to overcome those issues with the new Portable Stimulus Standard in this DMA-based case study.

Guides

  • Portable stimulus

    EDA - Standards, Technologies

    Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.

  • Dynamic power optimization

    EDA - Techniques

    FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.

  • Monolithic 3DIC for SoC

    EDA - Technologies

    Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.

Expert Insights

Ashish Darbari

Doc Formal: Introducing the ADEPT FV flow

Ashish Darbari is CEO of formal verification consultancy Axiomise.

Escape formal's narrower definitions with a flow that shows you how to Avoid, Detect, Erase, Prove Absence and Tape Out while avoiding bugs.

Rahul Chirania

Verifying clock domain crossings in UPF-based low-power SoCs

The verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.

Morten Christiansen

Understanding USB 3.2 and Type-C

The basics of USB 3.2, how to implement it in an SoC, and how USB Type-C connectors and cables are used in USB 3.2 systems.

EDA

  1. Philip Vanness is a product marketing manager at Mentor, a Siemens business.
    Expert Insight 8.8 billion miles to verify

    How the digital twin can fuel automotive verification flows impossible in the real world.

  2. Article Reliability verification: It’s all about the baseline
  3. Article How to improve throughput for gate-level simulation

PCB

  1. PCI_Express_logo
    Article Tackling the design challenges of PCIe 5.0

    Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.

  2. Article How Channel Operating Margin helps Gigabit Ethernet PCB analysis
  3. Expert Insight The Wally Rhines interview – Part Two: AI, automotive and security

IP

  1. Article The antifuse advantage for one-time programmable non-volatile memory

    Antifuse-based OTP NVM is highly scalable, has the area efficiency to enable macros  of megabit capacities, and offers low read power.

  2. Expert Insight Why AI needs security
  3. Article Using threat models and risk assessments to define device security requirements

Embedded

  1. Allen Watson of Synopsys
    Expert Insight An open-source framework for greater flexibility in machine-learning development

    Exchange frameworks are emerging to make it easier for neural-network developers to swap between development environments.

  2. Expert Insight Flexible embedded vision processing architectures for machine-learning applications
  3. Article Managing the evolving architecture of integrated ADAS controllers

Briefing

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