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How Starblaze combined simulation and emulation to design SSD controller firmware

This case study describes how the Beijing-based start-up realized its T10 Plus SSD controller using a simultaneous flow.

Guides

  • Portable stimulus

    EDA - Standards, Technologies

    Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.

  • Dynamic power optimization

    EDA - Techniques

    FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.

  • Monolithic 3DIC for SoC

    EDA - Technologies

    Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.

Expert Insights

Gordon Cooper

Flexible embedded vision processing architectures for machine-learning applications

Gordon Cooper

Machine-learning strategies for embedded vision are evolving so quickly that designers need access to flexible, heterogenous processor architectures that can adapt as the algorithms evolve.

Gandharv Bhatara

EUV’s arrival demands a new resolution enhancement flow

Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.

Ashish Darbari

Doc Formal: Achieving exhaustive formal verification of packet-based designs

Ashish Darbari breaks down formal's value to this challenging verification task with code examples and reference to VC Formal from Synopsys.

EDA

  1. Dina Medhat is a Technical Lead for Calibre Design Solutions at Mentor, a Siemens Business. She has held a variety of product and technical marketing roles at the company, and received her BS and MS degrees from Ain Shames University in Cairo, Egypt. She is currently a PhD student at Ain Shames University.
    Expert Insight Managing waivers in reliability verification

    Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.

  2. Expert Insight The budget case for formal verification
  3. Expert Insight Formal fundamentals: what’s hiding behind your constraints

PCB

  1. PCI_Express_logo
    Article Tackling the design challenges of PCIe 5.0

    Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.

  2. Article How Channel Operating Margin helps Gigabit Ethernet PCB analysis
  3. Expert Insight The Wally Rhines interview – Part Two: AI, automotive and security

IP

  1. Visual: cars speeding along a road
    Article Managing the evolving architecture of integrated ADAS controllers

    Designers need to understand how the architecture of electronic control units used to implement ADAS in vehicles is changing.

  2. Expert Insight Picking the right-sized crypto processor for your SoC
  3. Article Bringing Ethernet time-sensitive networking to automotive applications

Embedded

  1. Expert Insight How emulation’s SoC and SoS advantages begin with transaction-based co-modeling

    An introduction to how virtual emulation has fueled the application of co-modeling for complex design verification.

  2. Expert Insight The impact of AI on autonomous vehicles
  3. Expert Insight How eFPGAs will help build the brave new world of AI

Briefing

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