Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
The second part of this feature looks at how Wave Computing's objectives with its dataflow processing unit for AI mapped to the use of emulation in its development.
An increasing number of AI players are building their own silicon and finding that emulation is key to overcoming the major challenges.
Escape formal's narrower definitions with a flow that shows you how to Avoid, Detect, Erase, Prove Absence and Tape Out while avoiding bugs.
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A detailed dive into how MBH strategies for litho hotspots have been enhanced to deal with double patterning at 20nm and below.
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Article Tackling the design challenges of PCIe 5.0
Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.
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Article Optimizing the hardware implementation of machine learning algorithms
Optimizing the way in which machine learning algorithms are implemented in hardware will be a major differentiator for SoCs, especially for edge devices.
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Article Using threat models and risk assessments to define device security requirements
The proliferation of attacks against embedded systems is making designers realize that they need to do more to secure their products and ecosystems.
- Expert Insight An open-source framework for greater flexibility in machine-learning development
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