Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
A static-analysis tool that checks for errors in HDL code, lint is becoming an increasingly important addition to simulation for RTL and SoC signoff.
Hierarchical DFT is vital for large, complex designs. Users still to transition to the technique can nevertheless exploit its pattern reuse strategies as they move toward adoption.
Using formal core coverage to understand the effectiveness of formal coverage verification strategies in SoC design.
DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).
Expert Insight The art of abstraction
Successful FPV of large designs requires that parts of the design are abstracted. Learning how and where to apply abstractions will result in more proven properties and more bugs found.
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Article Teaching computers to recognize a smile (or frown, or grimace or…)
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