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Real Intent hierarchical CDC

Hierarchy provides a smarter approach to SoC CDC verification

Performing clock-domain crossing (CDC) checks on a flat database is difficult on complex SoCs. Hierarchy improves speed but calls for a smarter approach.

Guides

  • Interconnect resistance

    EDA - Techniques

    A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.

  • Cell pin access

    EDA - Techniques

    Increasingly complex design rules in 14nm and 16nm make it harder to connect local routing to the inputs and outputs (pins) of standard cells.

  • X propagation

    EDA - Techniques

    X propagation within RTL simulations can hide fatal bugs. Uncovering and eliminating the effect improves design quality and avoids respins.

Expert Insights

Pranav Ashar

Reset optimization pays big dividends before simulation

Pranav Ashar

Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.

Randall Myers

Straighten up and fly right

Fighter pilots have long trusted highly sophisticated automation. That’s how you can meet the challenges posed by advanced PCB design techniques.

Joe Kwan

Standard cell IP must pass the litho-friendly routing test

Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.

EDA

  1. Chris Tice is corporate vice president and general manager of hardware system verification at Cadence Design Systems
    Expert Insight The rise of hardware-assisted verification

    Verification of hardware and software has become a key bottleneck for chip design. Hardware-assisted verification is removing that bottleneck.

  2. Expert Insight Next wave of innovation in verification technology must come from integration
  3. Article Catching X-propagation related issues at RTL

PCB

  1. Julian Coates is the director of business development for Mentor Graphics Valor division.
    Expert Insight Make best-practice lean NPI for PCB a reality

    Shifting DFM validation earlier in the flow speeds NPI, cuts respins and gives you a critical edge.

  2. Expert Insight Henny Youngman’s advice to PCB designers
  3. Expert Insight IPC-2581 transfer standard gains momentum

IP

  1. Neil Songcuan is a senior product marketing manager, responsible for the FPGA-based Prototyping Solution at Synopsys.
    Expert Insight Using HAPS to streamline IP to SoC integration

    The HAPS prototyping system can help designers integrate IP into SoCs more quickly.

  2. Expert Insight Consistency key to gaining the advantages of IP integration
  3. Article FPGA-based prototyping to validate the integration of IP into an SoC

Embedded

  1. Featured image - virtual prototyping big.Little case study
    Article Debugging with virtual prototypes – Part Four

    The fourth installment discusses the extra levels of debug capability available when using virtual prototypes through the example of an ARM big.LITTLE-based embedded system.

  2. Expert Insight Power management in embedded systems – new thinking required
  3. Article Debugging with virtual prototypes – Part Three

Briefing

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