Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
The assumption has been that extra security eats into profit margins. But with some lateral thinking it can actually improve the bottom line.
Doc Formal concludes his introduction to formal verification with a practitioner's view of the technology.
Using VESA's Display Stream Compression (DSC) standard to enable visually lossless performance and low latency for ultra-high-definition displays.
Article Your next node: find lithography issues early with DTCO
Pattern-based design/technology co-optimization (DTCO) estimates lithographic difficulty during the early stages of a new process technology node.
- Article Automating test from IP to SoC levels with portable stimulus
- Expert Insight Doc Formal: The evolution of formal verification – Part One
Expert Insight The Wally Rhines interview – Part Two: AI, automotive and security
This second part looks at Mentor’s views on flow neutrality, how DRS360 was born, machine learning and the threat from embedded Trojans.
- Article The basic PCB rules for a successful IoT design
- Expert Insight A reliability checklist for the Connected World
Article Combining USB Type-C and DisplayPort support in portable implementations
Using USB Type-C connectors to combine both USB-C 3.1 and DisplayPort data streams, to support data, audio, video and power connections on a single port
- Expert Insight Using CCIX to implement cache coherent heterogeneous multiprocessor systems
- Expert Insight High-resolution visual recognition needs high-performance CNNs
Article Applying sub-threshold circuit techniques to IoT device design
Operating at near-threshold or sub-threshold voltages reduces static and dynamic power consumption, at the cost of design complexity.
- Article Staging virtual prototype bring-up for faster software development
- Expert Insight Building faster data centers with 25G Ethernet
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