Latest
Enhanced model-based hinting may be the edge you need below 20nm
A detailed dive into how MBH strategies for litho hotspots have been enhanced to deal with double patterning at 20nm and below.-
Win on the fault campaign trail with formal
Adding system-level, post-layout electrical analysis to HDAP design and verification
Reliability verification: It’s all about the baseline
Guides
-
Portable stimulus
Accellera’s Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
-
Dynamic power optimization
FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
-
Monolithic 3DIC for SoC
Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
Expert Insights
Doc Formal: Introducing the ADEPT FV flow
Escape formal's narrower definitions with a flow that shows you how to Avoid, Detect, Erase, Prove Absence and Tape Out while avoiding bugs.
Verifying clock domain crossings in UPF-based low-power SoCs
The verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
Understanding USB 3.2 and Type-C
The basics of USB 3.2, how to implement it in an SoC, and how USB Type-C connectors and cables are used in USB 3.2 systems.
EDA
-
Expert Insight 8.8 billion miles to verify
How the digital twin can fuel automotive verification flows impossible in the real world.
- Article How to improve throughput for gate-level simulation
- Expert Insight An open-source framework for greater flexibility in machine-learning development
PCB
-
Article Tackling the design challenges of PCIe 5.0
Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.
- Article How Channel Operating Margin helps Gigabit Ethernet PCB analysis
- Expert Insight The Wally Rhines interview – Part Two: AI, automotive and security
IP
-
Article
The antifuse advantage for one-time programmable non-volatile memory
Antifuse-based OTP NVM is highly scalable, has the area efficiency to enable macros of megabit capacities, and offers low read power.
- Expert Insight Why AI needs security
- Article Using threat models and risk assessments to define device security requirements
Embedded
-
Expert Insight Flexible embedded vision processing architectures for machine-learning applications
Machine-learning strategies for embedded vision are evolving so quickly that designers need access to flexible, heterogenous processor architectures that can adapt as the algorithms evolve.
- Article Managing the evolving architecture of integrated ADAS controllers
- Article Bringing Ethernet time-sensitive networking to automotive applications
PLATINUM SPONSORS
View All Sponsors