A DVCon technical paper addresses potential reset domain crossing metastability issues due to UPF instrumentation.
In Las Vegas, the parser specialist will demonstrate its tools for EDA software development across VHDL, SystemVerilog and UPF.
Verific Design Automation , specialist in parsers for SystemVerilog, VHDL and UPF, will also demo its INVIO platform with high level Python and C++ APIs.
The parser specialist will demonstrate its recently announced INVIO integration to speed development around VHDL and SystemVerilog.
UPF power state tables have become unwieldy due to rapid growth in LP design. The new construct, 'add_power_state' enables better verification flows.
Parser specialist will highlight work with a low power startup and new features for platforms supporting UPF.
Mentor Graphics chairman and CEO Wally Rhines will deliver the DVCon keynote as the vendor sets a deep agenda for the conference.
The latest update to the CustomSim FastSpice tool from Synopsys provides more consistent speedups from multicore workstations and adds support for BCD processes and real-number modeling.
Focus on systemic issues matches DVCon Europe event to European interests
Cadence Design Systems has developed an FPGA-based prototyping system that takes advantage of much closer alignment with its existing Palladium XP emulator to accelerate bring-up and support debugging across both platforms.
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