UPF

May 20, 2019

DAC 2019 preview: Verific Design Automation

In Las Vegas, the parser specialist will demonstrate its tools for EDA software development across VHDL, SystemVerilog and UPF.
Article  |  Topics: Conferences, Blog - EDA, - Tool development, Verification  |  Tags: , , , ,   |  Organizations: ,
February 21, 2019

DVCon USA 2019 preview: Verific Design Automation

Verific Design Automation , specialist in parsers for SystemVerilog, VHDL and UPF, will also demo its INVIO platform with high level Python and C++ APIs.
Article  |  Topics: Blog - EDA, - Tool development  |  Tags: , , , , , ,   |  Organizations: ,
June 18, 2018

DAC 2018 preview: Verific

The parser specialist will demonstrate its recently announced INVIO integration to speed development around VHDL and SystemVerilog.
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations:
December 6, 2017

Learn how to simplify power states in UPF

UPF power state tables have become unwieldy due to rapid growth in LP design. The new construct, 'add_power_state' enables better verification flows.
Article  |  Topics: Blog - EDA, - Standards, Verification  |  Tags: , , ,   |  Organizations: , , ,
June 9, 2017

DAC 2017 preview: Verific Design Automation

Parser specialist will highlight work with a low power startup and new features for platforms supporting UPF.
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations: ,
February 22, 2016

DVCon United States 2016 preview: Mentor Graphics

Mentor Graphics chairman and CEO Wally Rhines will deliver the DVCon keynote as the vendor sets a deep agenda for the conference.
June 29, 2015

FastSpice update improves parallelism and adds wreal support

The latest update to the CustomSim FastSpice tool from Synopsys provides more consistent speedups from multicore workstations and adds support for BCD processes and real-number modeling.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
September 3, 2014

DVCon Europe focuses on systems design and verification

Focus on systemic issues matches DVCon Europe event to European interests
Article  |  Topics: Conferences, Verification  |  Tags: , , , ,   |  Organizations:
July 17, 2014

Cadence brings FPGA prototyping and emulation into sync

Cadence Design Systems has developed an FPGA-based prototyping system that takes advantage of much closer alignment with its existing Palladium XP emulator to accelerate bring-up and support debugging across both platforms.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , ,   |  Organizations:
March 26, 2014

Synopsys strengthens analog and mixed-signal verification with VCS AMS

VCS AMS updates AMS verification tool and methodology
Article  |  Topics: Verification  |  Tags: , ,   |  Organizations:

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