DVCon

There is no comprehensive standard yet for functional coverage across designs using SystemC, TLM, UVM and SystemVerilog, but there are options using UVM Connect.

A panel at DVCon argued too much of a focus on point tools coupled with challenges with interoperability and cross-industry cooperation is hindering the ability of SoC teams to design and verify complex products.

DVCon US 2020 is to end a day early as a result of the COVID-19 coronavirus outbreak and released an updated agenda.

Portable stimulus pioneer Breker will feature across the DVCon program also highlighting its work with RISC-V.

The Electronic System Design Alliance will discuss the benefits it offers for design and verification, and has added Avery Design Systems.

Tool development specialist Verific will demonstrate its parsers and their integration with INVIO APIs.

Mentor will have a very broad presence at DVCon across technologies such as HLS, formal verification, simulation and emulation.

A new CDC methodology uses automation and data hooks to improve a notoriously lengthy and tricky task - verifying synchronizers.

Emulation is already playing a vital role in advanced automotive design within a digital twin environment.

The third part of this series takes the original CNN demonstrator through a full ISO 26262 type functional safety workflow