DVCon

April 17, 2023

Achieving functional coverage of multi-language designs

There is no comprehensive standard yet for functional coverage across designs using SystemC, TLM, UVM and SystemVerilog, but there are options using UVM Connect.
March 4, 2022

Verification engineers look to better skills to beat schedules

A panel at DVCon argued too much of a focus on point tools coupled with challenges with interoperability and cross-industry cooperation is hindering the ability of SoC teams to design and verify complex products.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: , , ,
March 3, 2020

DVCon US 2020: Coronavirus program changes

DVCon US 2020 is to end a day early as a result of the COVID-19 coronavirus outbreak and released an updated agenda.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: ,   |  Organizations: ,
February 27, 2020

DVCon US 2020 preview: Breker Verification Systems

Portable stimulus pioneer Breker will feature across the DVCon program also highlighting its work with RISC-V.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , ,   |  Organizations: ,
February 26, 2020

DVCon US 2020 preview: ESD Alliance

The Electronic System Design Alliance will discuss the benefits it offers for design and verification, and has added Avery Design Systems.
Article  |  Topics: Conferences, Blog - EDA, - Industry Blogs  |  Tags:   |  Organizations: , , ,
February 26, 2020

DVCon US 2020 preview: Verific

Tool development specialist Verific will demonstrate its parsers and their integration with INVIO APIs.
Article  |  Topics: Blog Topics, Conferences, Blog - EDA, - Tool development, Verification  |  Tags: , , , , ,   |  Organizations: ,
February 24, 2020

DVCon US 2020 preview: Mentor

Mentor will have a very broad presence at DVCon across technologies such as HLS, formal verification, simulation and emulation.
Article  |  Topics: Blog - EDA, - HLS, Next Generation Design, Standards, Verification  |  Tags:   |  Organizations: ,
December 17, 2019

Automating the pain out of clock domain crossing verification

A new CDC methodology uses automation and data hooks to improve a notoriously lengthy and tricky task - verifying synchronizers.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , ,   |  Organizations: ,
October 7, 2019

Master the design and verification of next gen transport: Part Four – emulation

Emulation is already playing a vital role in advanced automotive design within a digital twin environment.
October 4, 2019

Master the design and verification of next gen transport: Part Three – functional safety

The third part of this series takes the original CNN demonstrator through a full ISO 26262 type functional safety workflow

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