Using VESA's Display Stream Compression (DSC) standard to enable visually lossless performance and low latency for ultra-high-definition displays.
CCIX is a cache coherency protocol, based on PCI Express, for interconnecting high-performance heterogenous multiprocessing systems.
Quadrupling the performance of a dedicated CNN engine within an embedded vision processing core brings more complex graph processing within reach.
SoC developers who want to use USB Type-C in their designs will have to implement HDCP 2.2 content protection so that the target devices will be able to play protected content.
The increasing complexity of human-machine interfaces is challenging processor designers to produce the necessary performance within a limited power budget
The rising bandwidth demands of data centres have driven the development of 25G Ethernet, which will also form a pathway to 100G.
Addressing the challenge of achieving ASIL D certification of the functional safety of an SoC for use in the safety-critical path of an automotive system.
To check the connectivity of an SoC, first you have to define what a connection is...
A look at the steps necessary to validate implementations of the cryptographic algorithms that are used to protect today’s devices and communications infrastructure.
USB 2.0 could become an integration standard for IoT SoCs, due to its ubiquity, available drivers, support for rapid prototyping, and area efficiency.
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