enterprise verification platform

February 15, 2017

DVCon US 2017 preview: Mentor Graphics

The major verification conference is looming and Mentor's participation will include tutorials that explore the latest in portable stimulus, SystemC, VIP and more.

Article | Topics: Conferences, Blog - EDA, - Verification | Tags: enterprise verification platform, functional verification, portable stimulus, systemc, UVM, verification IP | Organizations: Accellera, Breker Verification Systems, Cadence Design Systems, DVCon, Intel, Mentor Graphics, Microsemi, NXP Semiconductors, Synopsys

March 1, 2016

Mentor builds out verification IP for memory

About 1,600 new UVM System Verilog verification IP memory models will cut testbench development time and offer more time to increase coverage.

Article | Topics: Blog - EDA, IP, - Tested Component to System, Verification | Tags: DRAM, enterprise verification platform, flash, hyperbus, Questa, SystemVerilog, test bench, test case, UCIS, UVM, verification IP | Organizations: Cypress Semiconductor, Mentor Graphics

February 22, 2016

DVCon United States 2016 preview: Mentor Graphics

Mentor Graphics chairman and CEO Wally Rhines will deliver the DVCon keynote as the vendor sets a deep agenda for the conference.

Article | Topics: Conferences, Blog - EDA, - Verification | Tags: Catapult, coverage, emulation, enterprise verification platform, EVP, formal verification, functional verification, low power, Power Pro, Questa, safety, security, UPF, UVM, validation, veloce, Visualizer | Organizations: Accellera, Arm, DVCon, Intel, Mentor Graphics, Qualcomm