verification

May 26, 2020

DVCon 2020 to repeat sessions online

DVCon US is to repeat sessions online from today until the middle of August, with exclusive access to registered attendees through early June.
Article  |  Topics: Blog - EDA, IP  |  Tags: ,   |  Organizations:
April 1, 2020

Coronavirus Resources: OneSpin Solutions

The verification specialist is adding more online resources to help engineers working from home during the Covid-19 pandemic.
Article  |  Topics: Blog Topics, Blog - EDA, - Verification  |  Tags: , , , ,   |  Organizations:
December 10, 2019

Breker adds automated system integration test generation for RISC-V

App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.
October 14, 2019

DVCon Europe looks to software for next phase in verification

October's DVCon Europe conference will have an increased focus on the role of software in electronic systems and the challenges it poses to verification.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
September 5, 2019

DVCon keynotes to look at edge computing and network evolution

DVCon Europe, Accellera’s design and verification conference to be held in Munich in late October, will feature keynotes on the trends toward edge computing and the future of networks.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:
July 31, 2019

Accellera sets up public code repository

Accellera has set up a public repository for the source code and other supplemental material needed for its standards.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
April 26, 2019

The evolution of the digital twin

A digital twin is now more than just a virtual copy of a product. For Siemens, it is a multilayered concept powering a 'boundary-free innovation platform'.
Article  |  Topics: Commentary, Conferences, Blog - EDA, PCB  |  Tags: , , , ,   |  Organizations: , ,
April 24, 2019

May meeting to push for UVM analog extensions

Accellera is trying to standardize extensions to UVM for mixed-signal design.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations:
March 26, 2019

DVCon Europe looks to software in call for papers

DVCon Europe has added embedded software, digital twin, machine learning, and RISC-V to the topics the conference organizers want to cover.
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , , , ,   |  Organizations:
February 21, 2019

DVCon USA 2019 preview: Metrics Technologies

Metrics Technologies demonstrate its cloud-based platform for ASIC and complex FPGA verification and discuss a new partnership with Concept Engineering.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , ,   |  Organizations: ,

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