verification

October 14, 2019

DVCon Europe looks to software for next phase in verification

October's DVCon Europe conference will have an increased focus on the role of software in electronic systems and the challenges it poses to verification.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
September 5, 2019

DVCon keynotes to look at edge computing and network evolution

DVCon Europe, Accellera’s design and verification conference to be held in Munich in late October, will feature keynotes on the trends toward edge computing and the future of networks.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations:
July 31, 2019

Accellera sets up public code repository

Accellera has set up a public repository for the source code and other supplemental material needed for its standards.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
April 26, 2019

The evolution of the digital twin

A digital twin is now more than just a virtual copy of a product. For Siemens, it is a multilayered concept powering a 'boundary-free innovation platform'.
Article  |  Topics: Commentary, Conferences, Blog - EDA, PCB  |  Tags: , , , ,   |  Organizations: , ,
April 24, 2019

May meeting to push for UVM analog extensions

Accellera is trying to standardize extensions to UVM for mixed-signal design.
Article  |  Topics: Blog - EDA, IP  |  Tags: , ,   |  Organizations:
March 26, 2019

DVCon Europe looks to software in call for papers

DVCon Europe has added embedded software, digital twin, machine learning, and RISC-V to the topics the conference organizers want to cover.
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , , , ,   |  Organizations:
February 21, 2019

DVCon USA 2019 preview: Metrics Technologies

Metrics Technologies demonstrate its cloud-based platform for ASIC and complex FPGA verification and discuss a new partnership with Concept Engineering.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , ,   |  Organizations: ,
November 13, 2018

Accellera updates UVM reference implementation

Accellera has updated the reference implementation for the Universal Verification Methodology to reflect the changes made for the latest release of the standard.
Article  |  Topics: Blog - EDA  |  Tags: ,   |  Organizations:
October 17, 2018

DVCon Europe takes in machine learning and stimulus for verification

Next week's DVCon Europe conference in Munich will tackle a range of topics, from analog verification to the use of machine learning for functional verification, backed up with case studies on the use of TLM and SystemC in live projects.
Article  |  Topics: Blog - EDA  |  Tags: , , ,
August 2, 2018

Mentor as a maturing Siemens business: 2. Foundations

How are Siemens' internal investments in Mentor to fuel innovation and integration stacking up alongside the boost it has given for M&A?
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations:

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