verification

August 17, 2020

Cadence uses machine learning to trim constrained-random runtimes

Cadence has developed a stimulus optimizer based on neural networks to try to improve the runtime of constrained-random verification runs.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
July 27, 2020

Open and propietary verification tools home in on RISC-V core quality

DAC provided a forum for the growing number of verification efforts focused on checking the architectural compliance and overall RTL quality of RISC-V processors.
July 21, 2020

Breker packages up apps for RISC-V, security and AI

Breker has added a number of specialized apps to its library that deal with the verification of RISC-V processors, secure enclaves, and machine-learning designs.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
July 20, 2020

Verifyter offers regression analysis for six months free

At DAC this week, Verifyter is offering a limited number of companies free six-month licences of its regression-analysis tool Pindown.
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July 7, 2020

DVCon Europe goes virtual

The organizers of DVCon Europe have decided to turn the autumn verification conference into a virtual event this year.
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May 26, 2020

DVCon 2020 to repeat sessions online

DVCon US is to repeat sessions online from today until the middle of August, with exclusive access to registered attendees through early June.
Article  |  Topics: Blog - EDA, IP  |  Tags: ,   |  Organizations:
April 1, 2020

Coronavirus Resources: OneSpin Solutions

The verification specialist is adding more online resources to help engineers working from home during the Covid-19 pandemic.
Article  |  Topics: Blog Topics, Blog - EDA, - Verification  |  Tags: , , , ,   |  Organizations:
December 10, 2019

Breker adds automated system integration test generation for RISC-V

App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.
October 14, 2019

DVCon Europe looks to software for next phase in verification

October's DVCon Europe conference will have an increased focus on the role of software in electronic systems and the challenges it poses to verification.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations:
September 5, 2019

DVCon keynotes to look at edge computing and network evolution

DVCon Europe, Accellera’s design and verification conference to be held in Munich in late October, will feature keynotes on the trends toward edge computing and the future of networks.
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