App joins Portable Stimulus specialist's Trek5 family to reduce manual test writing during verification on designs for the fast-growing RISC-V open-source processor.
October's DVCon Europe conference will have an increased focus on the role of software in electronic systems and the challenges it poses to verification.
DVCon Europe, Accellera’s design and verification conference to be held in Munich in late October, will feature keynotes on the trends toward edge computing and the future of networks.
Accellera has set up a public repository for the source code and other supplemental material needed for its standards.
A digital twin is now more than just a virtual copy of a product. For Siemens, it is a multilayered concept powering a 'boundary-free innovation platform'.
Accellera is trying to standardize extensions to UVM for mixed-signal design.
DVCon Europe has added embedded software, digital twin, machine learning, and RISC-V to the topics the conference organizers want to cover.
Metrics Technologies demonstrate its cloud-based platform for ASIC and complex FPGA verification and discuss a new partnership with Concept Engineering.
Accellera has updated the reference implementation for the Universal Verification Methodology to reflect the changes made for the latest release of the standard.
Next week's DVCon Europe conference in Munich will tackle a range of topics, from analog verification to the use of machine learning for functional verification, backed up with case studies on the use of TLM and SystemC in live projects.
View All Sponsors