verification

DVCon Europe is expanding coverage into research on design verification for its 10th conference later this year.

As first silicon success declines, new software aims to provide a more holistic view of coverage data from multiple sources.

The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.

The key to exploiting AI is being clear about where its family of technologies can help to improve and democratize design.

Aside from the keynotes and technical papers, the networking at an event like DVCon Europe provides a way to keep open-source EDA on the road.

DVCon Europe's keynotes will examine verification issues in connected cars and 5G networks.

Siemens EDA has launched a second version of its Symphony simulation environment designed to support quicker debug cycles.

DVCon Europe will be held as a live event in Munich in early December.

A panel at DVCon argued too much of a focus on point tools coupled with challenges with interoperability and cross-industry cooperation is hindering the ability of SoC teams to design and verify complex products.

Synopsys R&D vice president Manish Pandey described the ways in which the tools supplier has harnessed machine learning so far to gain speedups and improvements in coverage.