SystemVerilog

The board of directors of Accellera Systems Initiative has approved the 2023 edition of the Verilog-AMS standard for release.

Accellera has formed a working group to look at extensions to SystemVerilog to improve support for mixed-signal designs.

There is no comprehensive standard yet for functional coverage across designs using SystemC, TLM, UVM and SystemVerilog, but there are options using UVM Connect.

The tool development specialist will demonstrate its broad portfolio at next week's Design Automation Conference in San Francisco.

Variable lifetimes are an apparently basic but also tricky feature within the verification language.

Tool development enabler Verific will demonstrate its parsers, including a combination with the INVIO API platform at DAC 2021 in San Francisco next week.

Aldec updates tools to add support for the latest release of the VHDL verification methodology.

Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.

Arm works with EDA to find new efficiencies based on extra CTL-based check in Questa runs.

Sigasi has launched a software kit to provide inhouse tools builders and EDA vendors with a way to build in code-editing features.