Metrics Technologies demonstrate its cloud-based platform for ASIC and complex FPGA verification and discuss a new partnership with Concept Engineering.
Verific Design Automation , specialist in parsers for SystemVerilog, VHDL and UPF, will also demo its INVIO platform with high level Python and C++ APIs.
Testbench connections often depend on the virtual interface feature of SystemVerilog but other options - like abstract classes - can help.
With PSS moving toward greater adoption, the Siemens vendor seems PSS-DSL as a winner in terms of conciseness and ease-of-adoption.
After the moves by Cadence and Mentor, emulation in the cloud may only be the start of providing verification acceleration as a service.
The parser specialist will demonstrate its recently announced INVIO integration to speed development around VHDL and SystemVerilog.
Metrics Technologies has launched as a supplier of cloud-based verification tools offering per-minute pricing.
Sigasi has added support for SystemVerilog to its Sigasi Studio tool, which uses a built-in parser to perform more reliable syntax highlighting and error checking
Parser specialist will highlight work with a low power startup and new features for platforms supporting UPF.
DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.
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