SystemVerilog

December 11, 2020

OSVVM updates go into Riviera-Pro

Aldec updates tools to add support for the latest release of the VHDL verification methodology.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
December 1, 2020

Less than one-in-five FPGA projects avoid bug escapes (Wilson Functional Verification 2020 – Part Two)

Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.
July 30, 2020

Second formal check aids deadlock hunting

Arm works with EDA to find new efficiencies based on extra CTL-based check in Questa runs.
Article  |  Topics: Verification  |  Tags: , , , ,   |  Organizations: , ,
July 1, 2020

Sigasi creates SDK for custom editors

Sigasi has launched a software kit to provide inhouse tools builders and EDA vendors with a way to build in code-editing features.
Article  |  Topics: Blog - EDA  |  Tags: , , , , , ,   |  Organizations: ,
May 28, 2020

Coverage without tears

A technical paper originally presented at DVCon USA 2020 simplifies the creation of coverage strategies using manual, automated and verification IP components.
January 29, 2020

Toward more efficient formal strategies for deadlock

Deadlock is hard to detect even though there are formal strategies for doing so. But wouldn't it be better if you could automate that work? Now you can.
Article  |  Topics: Blog Topics, Verification  |  Tags: , , , , , ,   |  Organizations:
May 24, 2019

DAC 2019 Preview: Breker Verification Systems

The company will highlight features within its Trek suite that comply with but then go beyond the capabilities of the Portable Stimulus Standard.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , , , ,   |  Organizations: ,
May 20, 2019

DAC 2019 preview: Verific Design Automation

In Las Vegas, the parser specialist will demonstrate its tools for EDA software development across VHDL, SystemVerilog and UPF.
Article  |  Topics: Conferences, Blog - EDA, - Tool development, Verification  |  Tags: , , , ,   |  Organizations: ,
February 21, 2019

DVCon USA 2019 preview: Metrics Technologies

Metrics Technologies demonstrate its cloud-based platform for ASIC and complex FPGA verification and discuss a new partnership with Concept Engineering.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , ,   |  Organizations: ,
February 21, 2019

DVCon USA 2019 preview: Verific Design Automation

Verific Design Automation , specialist in parsers for SystemVerilog, VHDL and UPF, will also demo its INVIO platform with high level Python and C++ APIs.
Article  |  Topics: Blog - EDA, - Tool development  |  Tags: , , , , , ,   |  Organizations: ,

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