SystemVerilog

February 21, 2019

DVCon USA 2019 preview: Metrics Technologies

Metrics Technologies demonstrate its cloud-based platform for ASIC and complex FPGA verification and discuss a new partnership with Concept Engineering.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , ,   |  Organizations: ,
February 21, 2019

DVCon USA 2019 preview: Verific Design Automation

Verific Design Automation , specialist in parsers for SystemVerilog, VHDL and UPF, will also demo its INVIO platform with high level Python and C++ APIs.
Article  |  Topics: Blog - EDA, - Tool development  |  Tags: , , , , , ,   |  Organizations: ,
February 18, 2019

How to optimize your testbench-to-DUT connections

Testbench connections often depend on the virtual interface feature of SystemVerilog but other options - like abstract classes - can help.
December 28, 2018

Why Mentor backs the PSS-DSL input format for the Portable Stimulus Specification

With PSS moving toward greater adoption, the Siemens vendor seems PSS-DSL as a winner in terms of conciseness and ease-of-adoption.
Article  |  Topics: Verification  |  Tags: , , , , , ,   |  Organizations: ,
July 5, 2018

Cloud makes hardware acceleration more accessible

After the moves by Cadence and Mentor, emulation in the cloud may only be the start of providing verification acceleration as a service.
June 18, 2018

DAC 2018 preview: Verific

The parser specialist will demonstrate its recently announced INVIO integration to speed development around VHDL and SystemVerilog.
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations:
February 1, 2018

Metrics introduces elastic compute to handle peak-time verification

Metrics Technologies has launched as a supplier of cloud-based verification tools offering per-minute pricing.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
June 15, 2017

Smart code editor adds SystemVerilog support

Sigasi has added support for SystemVerilog to its Sigasi Studio tool, which uses a built-in parser to perform more reliable syntax highlighting and error checking
Article  |  Topics: Blog - EDA  |  Tags: , , ,
June 9, 2017

DAC 2017 preview: Verific Design Automation

Parser specialist will highlight work with a low power startup and new features for platforms supporting UPF.
Article  |  Topics: Blog Topics  |  Tags: , , ,   |  Organizations: ,
May 2, 2017

Wally Rhines looks beyond ‘endless verification’ to the system era

DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.

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