The introduction of the DDR4 memory-bus standard will allow system designers to meet aggressive performance targets for their next-generation systems. But the changes required to support the higher datarates of DDR4 place stringent demands on the PCB designer.
A coordinated design methodology fine-tunes chip-to-package PCB layout and routing that involves high-integration devices.
Complexity and the increasing use of thermal analysis software by non-expert designers demands new approaches for chip and PCB implementations.
Electrical rule checks (ERC) are now available to deal with increasing PCB design complexity, speed project delivery and protect the intellectual property within them.
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