static verification


June 20, 2019

The road to ES Design West: Systems

ES Design West was created to reflect integration, even elision of tasks across the semiconductor supply chain. Here's how the program reflects the trend.
May 5, 2017

Embedded developers learn to become agile

Can embedded projects that call for both custom hardware and software be agile? It's a question that a conference in early May organized by UK training company Feabhas sought to answer.
February 22, 2016

DVCon United States 2016 preview: Real Intent

Verification specialist's DVCon activities are headlined by a panel on emulation and static verification.
June 8, 2015

Synopsys to acquire Atrenta

Atrenta's SpyGlass line and others to be absorbed in Verification Continuum and Galaxy as part of EDA's latest major consolidation.
May 21, 2015

Real Intent tackles CDC at the physical level

Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.
September 29, 2014

Verification platform offers unified compile, debug environments

Synopsys is integrating its verification tools to make it easier to move between verification approaches for software centric SoCs
Article  |  Topics: Blog Topics, Verification  |  Tags: , , , , , , ,   |  Organizations:
July 22, 2014

Real Intent puts the accent on debug with new Ascent IIV release

More than 20 new features and improvements are added to the static functional tool.
Article  |  Topics: Product, RTL, Verification  |  Tags: , , , , ,   |  Organizations:
March 4, 2014

Synopsys targets 5X performance gain with integrated verification suite

New tool technologies, Verdi integration and greater flow concurrency also contribute to a claimed 3X increase in productivity for Verification Compiler.

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