Accellera has published for public review version 0.1 of a standard designed to help pass clock-domain crossing information between EDA tools.
A DVCon technical paper addresses potential reset domain crossing metastability issues due to UPF instrumentation.
ES Design West was created to reflect integration, even elision of tasks across the semiconductor supply chain. Here's how the program reflects the trend.
Can embedded projects that call for both custom hardware and software be agile? It's a question that a conference in early May organized by UK training company Feabhas sought to answer.
Verification specialist's DVCon activities are headlined by a panel on emulation and static verification.
Atrenta's SpyGlass line and others to be absorbed in Verification Continuum and Galaxy as part of EDA's latest major consolidation.
Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.
Synopsys is integrating its verification tools to make it easier to move between verification approaches for software centric SoCs
More than 20 new features and improvements are added to the static functional tool.
New tool technologies, Verdi integration and greater flow concurrency also contribute to a claimed 3X increase in productivity for Verification Compiler.
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