UVM

Tessolve is bringing its Verification Futures conference to the US with an event scheduled for mid-September.

There is no comprehensive standard yet for functional coverage across designs using SystemC, TLM, UVM and SystemVerilog, but there are options using UVM Connect.

Breker's presence at next week's Design Automation Conference (DAC) will emphasize a new collaboration around the RISC-V platform.

A panel at DVCon argued too much of a focus on point tools coupled with challenges with interoperability and cross-industry cooperation is hindering the ability of SoC teams to design and verify complex products.

Breker will highlight its latest work on stress-testing processor, storage and I/O architectures during DAC 2021 this week.

The best paper awards at this month's DVCon highlighted techniques to streamline verification. The European version in the meantime is looking for paper submissions.

October's DVCon Europe conference will have an increased focus on the role of software in electronic systems and the challenges it poses to verification.

The company will highlight features within its Trek suite that comply with but then go beyond the capabilities of the Portable Stimulus Standard.

Accellera is trying to standardize extensions to UVM for mixed-signal design.

Breker CEO Adnan Hamid will lead a tutorial on the Portable Stimulus Standard as part of the verification specialist's activities in Shanghai.