7nm

June 9, 2021

Xilinx retools Versal for high-end edge AI

Xilinx has reworked its Versal FPGA for edge-AI applications.
Article  |  Topics: Blog - Embedded, IP  |  Tags: , , , , ,   |  Organizations:
June 4, 2021

TSMC spins outs processes for automotive and RF

TSMC is developing processes for high-end automotive and RF based off its N5 and N7 families.
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September 14, 2020

Aprisa team to be doubled after Mentor purchase

Mentor, a Siemens business, plans to expand the team working on the Aprisa place-and-route tool following the purchase of Avatar Integrated Systems, announced in July.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
August 25, 2020

TSMC fills in sub-nodes as EUV gains ground

TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , , ,   |  Organizations: ,
July 29, 2020

Litho hotspot analysis gets machine-learning turbocharge

A Mentor-Samsung collaboration cuts the need for model-based analysis and speeds analysis runtime by as much as 20X.
August 27, 2019

GlobalFoundries takes aim at TSMC’s customers in patent action

GlobalFoundries is calling for imports of chips fabbed by TSMC into the US and Germany in multiple actions based on a list of 16 patents.
Article  |  Topics: Blog - IP  |  Tags: , , , ,   |  Organizations: , , ,
February 1, 2019

Fast process access gets Moortec onto 7nm

Early access to tools for new processes is helping Moortec deliver IP to determine the real-time health of on-chip circuits.
August 28, 2018

GlobalFoundries stops 7nm work to focus on existing processes

GlobalFoundries has decided to put development of its 7nm process on the backburner and focus on its existing finFET and FD-SOI processes.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , , ,   |  Organizations:
July 3, 2018

Fusion improves timing say Synopsys users

Early-access customers talked about their experiences with the Synopsys Fusion-based flow in a panel session at the DAC.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: , , , ,
June 25, 2018

Node-variant FinFET tweaks try to improve cost, performance

Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations: , ,

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